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Date:      Fri, 25 Dec 2015 14:25:49 +0000 (UTC)
From:      Dimitry Andric <dim@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org
Subject:   svn commit: r292726 - in vendor/llvm/dist: . autoconf bindings/go/llvm bindings/ocaml/llvm docs include/llvm-c include/llvm/CodeGen lib/CodeGen/AsmPrinter lib/CodeGen/SelectionDAG lib/IR lib/LTO li...
Message-ID:  <201512251425.tBPEPnO7012002@repo.freebsd.org>

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Author: dim
Date: Fri Dec 25 14:25:49 2015
New Revision: 292726
URL: https://svnweb.freebsd.org/changeset/base/292726

Log:
  Import llvm 3.7.1 release (r255217).

Added:
  vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.dbg.value.ll
  vendor/llvm/dist/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll
  vendor/llvm/dist/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
  vendor/llvm/dist/test/CodeGen/AMDGPU/trunc-store.ll
  vendor/llvm/dist/test/CodeGen/BPF/fi_ri.ll
  vendor/llvm/dist/test/CodeGen/BPF/undef.ll
  vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/addrspacecast.ll
  vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/extractelement.ll
  vendor/llvm/dist/test/CodeGen/Mips/micromips-zero-mat-uses.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/ctr-loop-tls-const.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/ctrloop-intrin.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
  vendor/llvm/dist/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/pr24546.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/pr25157.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/rlwimi-and-or-bits.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/select-i1-vs-i1.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/vsx-fma-mutate-trivial-copy.ll
  vendor/llvm/dist/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll
  vendor/llvm/dist/test/CodeGen/X86/pr24374.ll
  vendor/llvm/dist/test/CodeGen/X86/setcc-lowering.ll
  vendor/llvm/dist/test/DebugInfo/gvn.ll
  vendor/llvm/dist/test/LTO/X86/diagnostic-handler-noexit.ll
  vendor/llvm/dist/test/MC/ARM/directive-arch-semantic-action.s   (contents, props changed)
Modified:
  vendor/llvm/dist/CMakeLists.txt
  vendor/llvm/dist/CREDITS.TXT
  vendor/llvm/dist/autoconf/configure.ac
  vendor/llvm/dist/bindings/go/llvm/ir.go
  vendor/llvm/dist/bindings/ocaml/llvm/llvm_ocaml.c
  vendor/llvm/dist/configure
  vendor/llvm/dist/docs/ReleaseNotes.rst
  vendor/llvm/dist/include/llvm-c/Core.h
  vendor/llvm/dist/include/llvm/CodeGen/CommandFlags.h
  vendor/llvm/dist/lib/CodeGen/AsmPrinter/WinException.cpp
  vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
  vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  vendor/llvm/dist/lib/IR/AsmWriter.cpp
  vendor/llvm/dist/lib/IR/Core.cpp
  vendor/llvm/dist/lib/LTO/LTOCodeGenerator.cpp
  vendor/llvm/dist/lib/MC/MCContext.cpp
  vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
  vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
  vendor/llvm/dist/lib/Target/AMDGPU/AMDGPURegisterInfo.td
  vendor/llvm/dist/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
  vendor/llvm/dist/lib/Target/AMDGPU/SIISelLowering.cpp
  vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.cpp
  vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.h
  vendor/llvm/dist/lib/Target/AMDGPU/SIInstructions.td
  vendor/llvm/dist/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp
  vendor/llvm/dist/lib/Target/AMDGPU/SIRegisterInfo.cpp
  vendor/llvm/dist/lib/Target/AMDGPU/SIRegisterInfo.h
  vendor/llvm/dist/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  vendor/llvm/dist/lib/Target/BPF/BPFISelDAGToDAG.cpp
  vendor/llvm/dist/lib/Target/BPF/BPFISelLowering.cpp
  vendor/llvm/dist/lib/Target/BPF/BPFInstrInfo.td
  vendor/llvm/dist/lib/Target/BPF/BPFRegisterInfo.cpp
  vendor/llvm/dist/lib/Target/Mips/MipsISelLowering.h
  vendor/llvm/dist/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPCAsmPrinter.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPCCTRLoops.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPCISelLowering.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPCInstrInfo.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPCInstrInfo.td
  vendor/llvm/dist/lib/Target/PowerPC/PPCInstrQPX.td
  vendor/llvm/dist/lib/Target/PowerPC/PPCInstrVSX.td
  vendor/llvm/dist/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
  vendor/llvm/dist/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
  vendor/llvm/dist/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
  vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp
  vendor/llvm/dist/lib/Transforms/IPO/PassManagerBuilder.cpp
  vendor/llvm/dist/lib/Transforms/Scalar/GVN.cpp
  vendor/llvm/dist/lib/Transforms/Utils/Local.cpp
  vendor/llvm/dist/test/CodeGen/BPF/sockex2.ll
  vendor/llvm/dist/test/MC/AMDGPU/vop3.s
  vendor/llvm/dist/test/MC/Sparc/sparc-directive-xword.s
  vendor/llvm/dist/tools/llvm-lto/llvm-lto.cpp
  vendor/llvm/dist/tools/llvm-shlib/Makefile
  vendor/llvm/dist/unittests/Transforms/Utils/Local.cpp

Modified: vendor/llvm/dist/CMakeLists.txt
==============================================================================
--- vendor/llvm/dist/CMakeLists.txt	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/CMakeLists.txt	Fri Dec 25 14:25:49 2015	(r292726)
@@ -60,7 +60,7 @@ set(CMAKE_MODULE_PATH
 
 set(LLVM_VERSION_MAJOR 3)
 set(LLVM_VERSION_MINOR 7)
-set(LLVM_VERSION_PATCH 0)
+set(LLVM_VERSION_PATCH 1)
 set(LLVM_VERSION_SUFFIX "")
 
 if (NOT PACKAGE_VERSION)

Modified: vendor/llvm/dist/CREDITS.TXT
==============================================================================
--- vendor/llvm/dist/CREDITS.TXT	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/CREDITS.TXT	Fri Dec 25 14:25:49 2015	(r292726)
@@ -509,3 +509,10 @@ N: Michael Wong
 E: fraggamuffin@gmail.com 
 D: Clang OpenMP implementation
 
+N: Alexander Mussman
+E: alexander.musman@intel.com 
+D: Clang OpenMP implementation
+
+N: Kevin O'Brien
+E: caomhin@us.ibm.com 
+D: Clang OpenMP implementation
\ No newline at end of file

Modified: vendor/llvm/dist/autoconf/configure.ac
==============================================================================
--- vendor/llvm/dist/autoconf/configure.ac	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/autoconf/configure.ac	Fri Dec 25 14:25:49 2015	(r292726)
@@ -32,11 +32,11 @@ dnl===----------------------------------
 dnl Initialize autoconf and define the package name, version number and
 dnl address for reporting bugs.
 
-AC_INIT([LLVM],[3.7.0],[http://llvm.org/bugs/])
+AC_INIT([LLVM],[3.7.1],[http://llvm.org/bugs/])
 
 LLVM_VERSION_MAJOR=3
 LLVM_VERSION_MINOR=7
-LLVM_VERSION_PATCH=0
+LLVM_VERSION_PATCH=1
 LLVM_VERSION_SUFFIX=
 
 AC_DEFINE_UNQUOTED([LLVM_VERSION_MAJOR], $LLVM_VERSION_MAJOR, [Major version of the LLVM API])

Modified: vendor/llvm/dist/bindings/go/llvm/ir.go
==============================================================================
--- vendor/llvm/dist/bindings/go/llvm/ir.go	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/bindings/go/llvm/ir.go	Fri Dec 25 14:25:49 2015	(r292726)
@@ -1728,7 +1728,7 @@ func (b Builder) CreatePtrDiff(lhs, rhs 
 func (b Builder) CreateLandingPad(t Type, personality Value, nclauses int, name string) (l Value) {
 	cname := C.CString(name)
 	defer C.free(unsafe.Pointer(cname))
-	l.C = C.LLVMBuildLandingPad(b.C, t.C, C.unsigned(nclauses), cname)
+	l.C = C.LLVMBuildLandingPad(b.C, t.C, nil, C.unsigned(nclauses), cname)
 	return l
 }
 

Modified: vendor/llvm/dist/bindings/ocaml/llvm/llvm_ocaml.c
==============================================================================
--- vendor/llvm/dist/bindings/ocaml/llvm/llvm_ocaml.c	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/bindings/ocaml/llvm/llvm_ocaml.c	Fri Dec 25 14:25:49 2015	(r292726)
@@ -1745,7 +1745,7 @@ CAMLprim LLVMValueRef llvm_build_invoke_
 CAMLprim LLVMValueRef llvm_build_landingpad(LLVMTypeRef Ty, LLVMValueRef PersFn,
                                             value NumClauses,  value Name,
                                             value B) {
-    return LLVMBuildLandingPad(Builder_val(B), Ty, Int_val(NumClauses),
+    return LLVMBuildLandingPad(Builder_val(B), Ty, PersFn, Int_val(NumClauses),
                                String_val(Name));
 }
 

Modified: vendor/llvm/dist/configure
==============================================================================
--- vendor/llvm/dist/configure	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/configure	Fri Dec 25 14:25:49 2015	(r292726)
@@ -1,6 +1,6 @@
 #! /bin/sh
 # Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.60 for LLVM 3.7.0.
+# Generated by GNU Autoconf 2.60 for LLVM 3.7.1.
 #
 # Report bugs to <http://llvm.org/bugs/>.
 #
@@ -561,8 +561,8 @@ SHELL=${CONFIG_SHELL-/bin/sh}
 # Identity of this package.
 PACKAGE_NAME='LLVM'
 PACKAGE_TARNAME='llvm'
-PACKAGE_VERSION='3.7.0'
-PACKAGE_STRING='LLVM 3.7.0'
+PACKAGE_VERSION='3.7.1'
+PACKAGE_STRING='LLVM 3.7.1'
 PACKAGE_BUGREPORT='http://llvm.org/bugs/'
 
 ac_unique_file="lib/IR/Module.cpp"
@@ -1333,7 +1333,7 @@ if test "$ac_init_help" = "long"; then
   # Omit some internal or obsolete options to make the list less imposing.
   # This message is too long to be a string in the A/UX 3.1 sh.
   cat <<_ACEOF
-\`configure' configures LLVM 3.7.0 to adapt to many kinds of systems.
+\`configure' configures LLVM 3.7.1 to adapt to many kinds of systems.
 
 Usage: $0 [OPTION]... [VAR=VALUE]...
 
@@ -1399,7 +1399,7 @@ fi
 
 if test -n "$ac_init_help"; then
   case $ac_init_help in
-     short | recursive ) echo "Configuration of LLVM 3.7.0:";;
+     short | recursive ) echo "Configuration of LLVM 3.7.1:";;
    esac
   cat <<\_ACEOF
 
@@ -1583,7 +1583,7 @@ fi
 test -n "$ac_init_help" && exit $ac_status
 if $ac_init_version; then
   cat <<\_ACEOF
-LLVM configure 3.7.0
+LLVM configure 3.7.1
 generated by GNU Autoconf 2.60
 
 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
@@ -1599,7 +1599,7 @@ cat >config.log <<_ACEOF
 This file contains any messages produced by compilers while
 running configure, to aid debugging if configure makes a mistake.
 
-It was created by LLVM $as_me 3.7.0, which was
+It was created by LLVM $as_me 3.7.1, which was
 generated by GNU Autoconf 2.60.  Invocation command line was
 
   $ $0 $@
@@ -1955,7 +1955,7 @@ ac_compiler_gnu=$ac_cv_c_compiler_gnu
 
 LLVM_VERSION_MAJOR=3
 LLVM_VERSION_MINOR=7
-LLVM_VERSION_PATCH=0
+LLVM_VERSION_PATCH=1
 LLVM_VERSION_SUFFIX=
 
 
@@ -8643,87 +8643,6 @@ fi
 
 if test "$llvm_cv_os_type" = "MingW" ; then
 
-{ echo "$as_me:$LINENO: checking for main in -limagehlp" >&5
-echo $ECHO_N "checking for main in -limagehlp... $ECHO_C" >&6; }
-if test "${ac_cv_lib_imagehlp_main+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-limagehlp  $LIBS"
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-
-int
-main ()
-{
-return main ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (ac_try="$ac_link"
-case "(($ac_try" in
-  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
-  *) ac_try_echo=$ac_try;;
-esac
-eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
-  (eval "$ac_link") 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag" || test ! -s conftest.err'
-  { (case "(($ac_try" in
-  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
-  *) ac_try_echo=$ac_try;;
-esac
-eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
-  (eval "$ac_try") 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (case "(($ac_try" in
-  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
-  *) ac_try_echo=$ac_try;;
-esac
-eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
-  (eval "$ac_try") 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_lib_imagehlp_main=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-	ac_cv_lib_imagehlp_main=no
-fi
-
-rm -f core conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
-fi
-{ echo "$as_me:$LINENO: result: $ac_cv_lib_imagehlp_main" >&5
-echo "${ECHO_T}$ac_cv_lib_imagehlp_main" >&6; }
-if test $ac_cv_lib_imagehlp_main = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define HAVE_LIBIMAGEHLP 1
-_ACEOF
-
-  LIBS="-limagehlp $LIBS"
-
-fi
-
-
 { echo "$as_me:$LINENO: checking for main in -lole32" >&5
 echo $ECHO_N "checking for main in -lole32... $ECHO_C" >&6; }
 if test "${ac_cv_lib_ole32_main+set}" = set; then
@@ -18610,7 +18529,7 @@ exec 6>&1
 # report actual input values of CONFIG_FILES etc. instead of their
 # values after options handling.
 ac_log="
-This file was extended by LLVM $as_me 3.7.0, which was
+This file was extended by LLVM $as_me 3.7.1, which was
 generated by GNU Autoconf 2.60.  Invocation command line was
 
   CONFIG_FILES    = $CONFIG_FILES
@@ -18663,7 +18582,7 @@ Report bugs to <bug-autoconf@gnu.org>."
 _ACEOF
 cat >>$CONFIG_STATUS <<_ACEOF
 ac_cs_version="\\
-LLVM config.status 3.7.0
+LLVM config.status 3.7.1
 configured by $0, generated by GNU Autoconf 2.60,
   with options \\"`echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\"
 

Modified: vendor/llvm/dist/docs/ReleaseNotes.rst
==============================================================================
--- vendor/llvm/dist/docs/ReleaseNotes.rst	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/docs/ReleaseNotes.rst	Fri Dec 25 14:25:49 2015	(r292726)
@@ -25,7 +25,35 @@ LLVM web page, this document applies to 
 one.  To see the release notes for a specific release, please see the `releases
 page <http://llvm.org/releases/>`_.
 
-Non-comprehensive list of changes in this release
+Major changes in 3.7.1
+======================
+
+* 3.7.0 was released with an inadvertent change to the signature of the C
+  API function: LLVMBuildLandingPad, which made the C API incompatible with
+  prior releases.  This has been corrected in LLVM 3.7.1.
+
+  As a result of this change, 3.7.0 is not ABI compatible with 3.7.1.
+
+  +----------------------------------------------------------------------------+
+  | History of the LLVMBuildLandingPad() function                              |
+  +===========================+================================================+
+  | 3.6.2 and prior releases  | LLVMBuildLandingPad(LLVMBuilderRef,            |
+  |                           |                     LLVMTypeRef,               |
+  |                           |                     LLVMValueRef,              |
+  |                           |                     unsigned, const char*)     |
+  +---------------------------+------------------------------------------------+
+  | 3.7.0                     | LLVMBuildLandingPad(LLVMBuilderRef,            |
+  |                           |                     LLVMTypeRef,               |
+  |                           |                     unsigned, const char*)     |
+  +---------------------------+------------------------------------------------+
+  | 3.7.1 and future releases | LLVMBuildLandingPad(LLVMBuilderRef,            |
+  |                           |                     LLVMTypeRef,               |
+  |                           |                     LLVMValueRef,              |
+  |                           |                     unsigned, const char*)     |
+  +---------------------------+------------------------------------------------+
+
+
+Non-comprehensive list of changes in 3.7.0
 =================================================
 
 .. NOTE

Modified: vendor/llvm/dist/include/llvm-c/Core.h
==============================================================================
--- vendor/llvm/dist/include/llvm-c/Core.h	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/include/llvm-c/Core.h	Fri Dec 25 14:25:49 2015	(r292726)
@@ -2675,7 +2675,8 @@ LLVMValueRef LLVMBuildInvoke(LLVMBuilder
                              LLVMBasicBlockRef Then, LLVMBasicBlockRef Catch,
                              const char *Name);
 LLVMValueRef LLVMBuildLandingPad(LLVMBuilderRef B, LLVMTypeRef Ty,
-                                 unsigned NumClauses, const char *Name);
+                                 LLVMValueRef PersFn, unsigned NumClauses,
+                                 const char *Name);
 LLVMValueRef LLVMBuildResume(LLVMBuilderRef B, LLVMValueRef Exn);
 LLVMValueRef LLVMBuildUnreachable(LLVMBuilderRef);
 

Modified: vendor/llvm/dist/include/llvm/CodeGen/CommandFlags.h
==============================================================================
--- vendor/llvm/dist/include/llvm/CodeGen/CommandFlags.h	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/include/llvm/CodeGen/CommandFlags.h	Fri Dec 25 14:25:49 2015	(r292726)
@@ -21,7 +21,7 @@
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/Module.h"
 #include "llvm/MC/MCTargetOptionsCommandFlags.h"
-#include "llvm//MC/SubtargetFeature.h"
+#include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Host.h"

Modified: vendor/llvm/dist/lib/CodeGen/AsmPrinter/WinException.cpp
==============================================================================
--- vendor/llvm/dist/lib/CodeGen/AsmPrinter/WinException.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/CodeGen/AsmPrinter/WinException.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -169,7 +169,7 @@ void WinException::endFunction(const Mac
     Asm->OutStreamer->PopSection();
   }
 
-  if (shouldEmitMoves)
+  if (shouldEmitMoves || shouldEmitPersonality)
     Asm->OutStreamer->EmitWinCFIEndProc();
 }
 

Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
==============================================================================
--- vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -439,7 +439,7 @@ ExpandUnalignedLoad(LoadSDNode *LD, Sele
                              ISD::ANY_EXTEND, dl, VT, Result);
 
       ValResult = Result;
-      ChainResult = Chain;
+      ChainResult = newLoad.getValue(1);
       return;
     }
 

Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
==============================================================================
--- vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -1010,6 +1010,8 @@ SDValue DAGTypeLegalizer::GetVectorEleme
 
   // Calculate the element offset and add it to the pointer.
   unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size.
+  assert(EltSize * 8 == EltVT.getSizeInBits() &&
+         "Converting bits to bytes lost precision");
 
   Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
                       DAG.getConstant(EltSize, dl, Index.getValueType()));

Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
==============================================================================
--- vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -1528,9 +1528,25 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXT
   if (CustomLowerNode(N, N->getValueType(0), true))
     return SDValue();
 
-  // Store the vector to the stack.
-  EVT EltVT = VecVT.getVectorElementType();
+  // Make the vector elements byte-addressable if they aren't already.
   SDLoc dl(N);
+  EVT EltVT = VecVT.getVectorElementType();
+  if (EltVT.getSizeInBits() < 8) {
+    SmallVector<SDValue, 4> ElementOps;
+    for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) {
+      ElementOps.push_back(DAG.getAnyExtOrTrunc(
+          DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec,
+                      DAG.getConstant(i, dl, MVT::i8)),
+          dl, MVT::i8));
+    }
+
+    EltVT = MVT::i8;
+    VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
+                             VecVT.getVectorNumElements());
+    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, ElementOps);
+  }
+
+  // Store the vector to the stack.
   SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
   SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
                                MachinePointerInfo(), false, false, 0);

Modified: vendor/llvm/dist/lib/IR/AsmWriter.cpp
==============================================================================
--- vendor/llvm/dist/lib/IR/AsmWriter.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/IR/AsmWriter.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -794,6 +794,10 @@ void SlotTracker::processFunction() {
   ST_DEBUG("begin processFunction!\n");
   fNext = 0;
 
+  // Process function metadata if it wasn't hit at the module-level.
+  if (!ShouldInitializeAllMetadata)
+    processFunctionMetadata(*TheFunction);
+
   // Add all the function arguments with no names.
   for(Function::const_arg_iterator AI = TheFunction->arg_begin(),
       AE = TheFunction->arg_end(); AI != AE; ++AI)
@@ -807,8 +811,6 @@ void SlotTracker::processFunction() {
     if (!BB.hasName())
       CreateFunctionSlot(&BB);
 
-    processFunctionMetadata(*TheFunction);
-
     for (auto &I : BB) {
       if (!I.getType()->isVoidTy() && !I.hasName())
         CreateFunctionSlot(&I);
@@ -836,11 +838,11 @@ void SlotTracker::processFunction() {
 
 void SlotTracker::processFunctionMetadata(const Function &F) {
   SmallVector<std::pair<unsigned, MDNode *>, 4> MDs;
-  for (auto &BB : F) {
-    F.getAllMetadata(MDs);
-    for (auto &MD : MDs)
-      CreateMetadataSlot(MD.second);
+  F.getAllMetadata(MDs);
+  for (auto &MD : MDs)
+    CreateMetadataSlot(MD.second);
 
+  for (auto &BB : F) {
     for (auto &I : BB)
       processInstructionMetadata(I);
   }

Modified: vendor/llvm/dist/lib/IR/Core.cpp
==============================================================================
--- vendor/llvm/dist/lib/IR/Core.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/IR/Core.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -2257,7 +2257,14 @@ LLVMValueRef LLVMBuildInvoke(LLVMBuilder
 }
 
 LLVMValueRef LLVMBuildLandingPad(LLVMBuilderRef B, LLVMTypeRef Ty,
-                                 unsigned NumClauses, const char *Name) {
+                                 LLVMValueRef PersFn, unsigned NumClauses,
+                                 const char *Name) {
+  // The personality used to live on the landingpad instruction, but now it
+  // lives on the parent function. For compatibility, take the provided
+  // personality and put it on the parent function.
+  if (PersFn)
+    unwrap(B)->GetInsertBlock()->getParent()->setPersonalityFn(
+        cast<Function>(unwrap(PersFn)));
   return wrap(unwrap(B)->CreateLandingPad(unwrap(Ty), NumClauses, Name));
 }
 

Modified: vendor/llvm/dist/lib/LTO/LTOCodeGenerator.cpp
==============================================================================
--- vendor/llvm/dist/lib/LTO/LTOCodeGenerator.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/LTO/LTOCodeGenerator.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -63,14 +63,21 @@ const char* LTOCodeGenerator::getVersion
 #endif
 }
 
+static void handleLTODiagnostic(const DiagnosticInfo &DI) {
+  DiagnosticPrinterRawOStream DP(errs());
+  DI.print(DP);
+  errs() << "\n";
+}
+
 LTOCodeGenerator::LTOCodeGenerator()
-    : Context(getGlobalContext()), IRLinker(new Module("ld-temp.o", Context)) {
+    : Context(getGlobalContext()), IRLinker(new Module("ld-temp.o", Context),
+                                            handleLTODiagnostic) {
   initializeLTOPasses();
 }
 
 LTOCodeGenerator::LTOCodeGenerator(std::unique_ptr<LLVMContext> Context)
     : OwnedContext(std::move(Context)), Context(*OwnedContext),
-      IRLinker(new Module("ld-temp.o", *OwnedContext)) {
+      IRLinker(new Module("ld-temp.o", *OwnedContext), handleLTODiagnostic) {
   initializeLTOPasses();
 }
 

Modified: vendor/llvm/dist/lib/MC/MCContext.cpp
==============================================================================
--- vendor/llvm/dist/lib/MC/MCContext.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/MC/MCContext.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -82,6 +82,7 @@ void MCContext::reset() {
 
   UsedNames.clear();
   Symbols.clear();
+  SectionSymbols.clear();
   Allocator.Reset();
   Instances.clear();
   CompilationDir.clear();

Modified: vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -264,6 +264,12 @@ void AMDGPUAsmPrinter::getSIProgramInfo(
   for (const MachineBasicBlock &MBB : MF) {
     for (const MachineInstr &MI : MBB) {
       // TODO: CodeSize should account for multiple functions.
+
+      // TODO: Should we count size of debug info?
+      if (MI.isDebugValue())
+        continue;
+
+      // FIXME: This is reporting 0 for many instructions.
       CodeSize += MI.getDesc().Size;
 
       unsigned numOperands = MI.getNumOperands();

Modified: vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -134,13 +134,17 @@ static Value* GEPToVectorIndex(GetElemen
 //
 // TODO: Check isTriviallyVectorizable for calls and handle other
 // instructions.
-static bool canVectorizeInst(Instruction *Inst) {
+static bool canVectorizeInst(Instruction *Inst, User *User) {
   switch (Inst->getOpcode()) {
   case Instruction::Load:
-  case Instruction::Store:
   case Instruction::BitCast:
   case Instruction::AddrSpaceCast:
     return true;
+  case Instruction::Store: {
+    // Must be the stored pointer operand, not a stored value.
+    StoreInst *SI = cast<StoreInst>(Inst);
+    return SI->getPointerOperand() == User;
+  }
   default:
     return false;
   }
@@ -166,7 +170,7 @@ static bool tryPromoteAllocaToVector(All
   for (User *AllocaUser : Alloca->users()) {
     GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(AllocaUser);
     if (!GEP) {
-      if (!canVectorizeInst(cast<Instruction>(AllocaUser)))
+      if (!canVectorizeInst(cast<Instruction>(AllocaUser), Alloca))
         return false;
 
       WorkList.push_back(AllocaUser);
@@ -184,7 +188,7 @@ static bool tryPromoteAllocaToVector(All
 
     GEPVectorIdx[GEP] = Index;
     for (User *GEPUser : AllocaUser->users()) {
-      if (!canVectorizeInst(cast<Instruction>(GEPUser)))
+      if (!canVectorizeInst(cast<Instruction>(GEPUser), AllocaUser))
         return false;
 
       WorkList.push_back(GEPUser);
@@ -240,7 +244,12 @@ static bool collectUsesWithPtrTypes(Valu
   for (User *User : Val->users()) {
     if(std::find(WorkList.begin(), WorkList.end(), User) != WorkList.end())
       continue;
-    if (isa<CallInst>(User)) {
+    if (CallInst *CI = dyn_cast<CallInst>(User)) {
+      // TODO: We might be able to handle some cases where the callee is a
+      // constantexpr bitcast of a function.
+      if (!CI->getCalledFunction())
+        return false;
+
       WorkList.push_back(User);
       continue;
     }
@@ -250,6 +259,12 @@ static bool collectUsesWithPtrTypes(Valu
     if (UseInst && UseInst->getOpcode() == Instruction::PtrToInt)
       return false;
 
+    if (StoreInst *SI = dyn_cast_or_null<StoreInst>(UseInst)) {
+      // Reject if the stored value is not the pointer operand.
+      if (SI->getPointerOperand() != Val)
+        return false;
+    }
+
     if (!User->getType()->isPointerTy())
       continue;
 

Modified: vendor/llvm/dist/lib/Target/AMDGPU/AMDGPURegisterInfo.td
==============================================================================
--- vendor/llvm/dist/lib/Target/AMDGPU/AMDGPURegisterInfo.td	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/AMDGPU/AMDGPURegisterInfo.td	Fri Dec 25 14:25:49 2015	(r292726)
@@ -14,8 +14,7 @@
 let Namespace = "AMDGPU" in {
 
 foreach Index = 0-15 in {
-  // Indices are used in a variety of ways here, so don't set a size/offset.
-  def sub#Index : SubRegIndex<-1, -1>;
+  def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
 }
 
 def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;

Modified: vendor/llvm/dist/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -71,12 +71,26 @@ void AMDGPUMCObjectWriter::writeObject(M
   }
 }
 
+static unsigned getFixupKindNumBytes(unsigned Kind) {
+  switch (Kind) {
+  case FK_Data_1:
+    return 1;
+  case FK_Data_2:
+    return 2;
+  case FK_Data_4:
+    return 4;
+  case FK_Data_8:
+    return 8;
+  default:
+    llvm_unreachable("Unknown fixup kind!");
+  }
+}
+
 void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
                                   unsigned DataSize, uint64_t Value,
                                   bool IsPCRel) const {
 
   switch ((unsigned)Fixup.getKind()) {
-    default: llvm_unreachable("Unknown fixup kind");
     case AMDGPU::fixup_si_sopp_br: {
       uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
       *Dst = (Value - 4) / 4;
@@ -96,6 +110,24 @@ void AMDGPUAsmBackend::applyFixup(const 
       *Dst = Value + 4;
       break;
     }
+    default: {
+      // FIXME: Copied from AArch64
+      unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
+      if (!Value)
+        return; // Doesn't change encoding.
+      MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
+
+      // Shift the value into position.
+      Value <<= Info.TargetOffset;
+
+      unsigned Offset = Fixup.getOffset();
+      assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
+
+      // For each byte of the fragment that the fixup touches, mask in the
+      // bits from the fixup value.
+      for (unsigned i = 0; i != NumBytes; ++i)
+        Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
+    }
   }
 }
 

Modified: vendor/llvm/dist/lib/Target/AMDGPU/SIISelLowering.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/AMDGPU/SIISelLowering.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/AMDGPU/SIISelLowering.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -157,6 +157,7 @@ SITargetLowering::SITargetLowering(Targe
 
   setTruncStoreAction(MVT::i64, MVT::i32, Expand);
   setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
+  setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
   setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
 
   setOperationAction(ISD::LOAD, MVT::i1, Custom);
@@ -2252,10 +2253,8 @@ MachineSDNode *SITargetLowering::buildSc
                                                   SDValue Ptr) const {
   const SIInstrInfo *TII =
       static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
-  uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | AMDGPU::RSRC_TID_ENABLE |
-                  0xffffffff; // Size
 
-  return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
+  return buildRSRC(DAG, DL, Ptr, 0, TII->getScratchRsrcWords23());
 }
 
 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,

Modified: vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -2778,3 +2778,16 @@ uint64_t SIInstrInfo::getDefaultRsrcData
 
   return RsrcDataFormat;
 }
+
+uint64_t SIInstrInfo::getScratchRsrcWords23() const {
+  uint64_t Rsrc23 = getDefaultRsrcDataFormat() |
+                    AMDGPU::RSRC_TID_ENABLE |
+                    0xffffffff; // Size;
+
+  // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
+  // Clear them unless we want a huge stride.
+  if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
+    Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT;
+
+  return Rsrc23;
+}

Modified: vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.h
==============================================================================
--- vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.h	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.h	Fri Dec 25 14:25:49 2015	(r292726)
@@ -353,7 +353,7 @@ public:
   }
 
   uint64_t getDefaultRsrcDataFormat() const;
-
+  uint64_t getScratchRsrcWords23() const;
 };
 
 namespace AMDGPU {

Modified: vendor/llvm/dist/lib/Target/AMDGPU/SIInstructions.td
==============================================================================
--- vendor/llvm/dist/lib/Target/AMDGPU/SIInstructions.td	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/AMDGPU/SIInstructions.td	Fri Dec 25 14:25:49 2015	(r292726)
@@ -1548,6 +1548,12 @@ defm V_WRITELANE_B32 : VOP2SI_3VI_m <
 // These instructions only exist on SI and CI
 let SubtargetPredicate = isSICI in {
 
+let isCommutable = 1 in {
+defm V_MAC_LEGACY_F32 : VOP2InstSI <vop2<0x6>, "v_mac_legacy_f32",
+  VOP_F32_F32_F32
+>;
+} // End isCommutable = 1
+
 defm V_MIN_LEGACY_F32 : VOP2InstSI <vop2<0xd>, "v_min_legacy_f32",
   VOP_F32_F32_F32, AMDGPUfmin_legacy
 >;
@@ -1562,12 +1568,6 @@ defm V_LSHL_B32 : VOP2InstSI <vop2<0x19>
 } // End isCommutable = 1
 } // End let SubtargetPredicate = SICI
 
-let isCommutable = 1 in {
-defm V_MAC_LEGACY_F32 : VOP2_VI3_Inst <vop23<0x6, 0x28e>, "v_mac_legacy_f32",
-  VOP_F32_F32_F32
->;
-} // End isCommutable = 1
-
 defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32",
   VOP_I32_I32_I32
 >;

Modified: vendor/llvm/dist/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -135,8 +135,7 @@ bool SIPrepareScratchRegs::runOnMachineF
       unsigned ScratchRsrcReg =
           RS.scavengeRegister(&AMDGPU::SReg_128RegClass, 0);
 
-      uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |
-                      0xffffffff; // Size
+      uint64_t Rsrc23 = TII->getScratchRsrcWords23();
 
       unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
       unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
@@ -152,11 +151,11 @@ bool SIPrepareScratchRegs::runOnMachineF
               .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
 
       BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc2)
-              .addImm(Rsrc & 0xffffffff)
+              .addImm(Rsrc23 & 0xffffffff)
               .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
 
       BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc3)
-              .addImm(Rsrc >> 32)
+              .addImm(Rsrc23 >> 32)
               .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
 
       // Scratch Offset

Modified: vendor/llvm/dist/lib/Target/AMDGPU/SIRegisterInfo.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/AMDGPU/SIRegisterInfo.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/AMDGPU/SIRegisterInfo.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -26,23 +26,25 @@ using namespace llvm;
 
 SIRegisterInfo::SIRegisterInfo() : AMDGPURegisterInfo() {}
 
-BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
-  BitVector Reserved(getNumRegs());
-  Reserved.set(AMDGPU::EXEC);
+void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
+  MCRegAliasIterator R(Reg, this, true);
 
-  // EXEC_LO and EXEC_HI could be allocated and used as regular register,
-  // but this seems likely to result in bugs, so I'm marking them as reserved.
-  Reserved.set(AMDGPU::EXEC_LO);
-  Reserved.set(AMDGPU::EXEC_HI);
+  for (; R.isValid(); ++R)
+    Reserved.set(*R);
+}
 
+BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+  BitVector Reserved(getNumRegs());
   Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
-  Reserved.set(AMDGPU::FLAT_SCR);
-  Reserved.set(AMDGPU::FLAT_SCR_LO);
-  Reserved.set(AMDGPU::FLAT_SCR_HI);
+
+  // EXEC_LO and EXEC_HI could be allocated and used as regular register, but
+  // this seems likely to result in bugs, so I'm marking them as reserved.
+  reserveRegisterTuples(Reserved, AMDGPU::EXEC);
+  reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
 
   // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
-  Reserved.set(AMDGPU::VGPR255);
-  Reserved.set(AMDGPU::VGPR254);
+  reserveRegisterTuples(Reserved, AMDGPU::VGPR254);
+  reserveRegisterTuples(Reserved, AMDGPU::VGPR255);
 
   // Tonga and Iceland can only allocate a fixed number of SGPRs due
   // to a hw bug.
@@ -54,10 +56,7 @@ BitVector SIRegisterInfo::getReservedReg
 
     for (unsigned i = Limit; i < NumSGPRs; ++i) {
       unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
-      MCRegAliasIterator R = MCRegAliasIterator(Reg, this, true);
-
-      for (; R.isValid(); ++R)
-        Reserved.set(*R);
+      reserveRegisterTuples(Reserved, Reg);
     }
   }
 

Modified: vendor/llvm/dist/lib/Target/AMDGPU/SIRegisterInfo.h
==============================================================================
--- vendor/llvm/dist/lib/Target/AMDGPU/SIRegisterInfo.h	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/AMDGPU/SIRegisterInfo.h	Fri Dec 25 14:25:49 2015	(r292726)
@@ -23,7 +23,10 @@
 namespace llvm {
 
 struct SIRegisterInfo : public AMDGPURegisterInfo {
+private:
+  void reserveRegisterTuples(BitVector &, unsigned Reg) const;
 
+public:
   SIRegisterInfo();
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;

Modified: vendor/llvm/dist/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/ARM/AsmParser/ARMAsmParser.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/ARM/AsmParser/ARMAsmParser.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -15,6 +15,7 @@
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCAssembler.h"
@@ -9104,6 +9105,10 @@ bool ARMAsmParser::parseDirectiveArch(SM
     return false;
   }
 
+  Triple T;
+  STI.setDefaultFeatures(T.getARMCPUForArch(Arch));
+  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
+
   getTargetStreamer().emitArch(ID);
   return false;
 }

Modified: vendor/llvm/dist/lib/Target/BPF/BPFISelDAGToDAG.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/BPF/BPFISelDAGToDAG.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/BPF/BPFISelDAGToDAG.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -50,6 +50,7 @@ private:
 
   // Complex Pattern for address selection.
   bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset);
+  bool SelectFIAddr(SDValue Addr, SDValue &Base, SDValue &Offset);
 };
 }
 
@@ -67,7 +68,7 @@ bool BPFDAGToDAGISel::SelectAddr(SDValue
       Addr.getOpcode() == ISD::TargetGlobalAddress)
     return false;
 
-  // Addresses of the form FI+const or FI|const
+  // Addresses of the form Addr+const or Addr|const
   if (CurDAG->isBaseWithConstantOffset(Addr)) {
     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
     if (isInt<32>(CN->getSExtValue())) {
@@ -89,6 +90,31 @@ bool BPFDAGToDAGISel::SelectAddr(SDValue
   return true;
 }
 
+// ComplexPattern used on BPF FI instruction
+bool BPFDAGToDAGISel::SelectFIAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
+  SDLoc DL(Addr);
+
+  if (!CurDAG->isBaseWithConstantOffset(Addr))
+    return false;
+
+  // Addresses of the form Addr+const or Addr|const
+  ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
+  if (isInt<32>(CN->getSExtValue())) {
+
+    // If the first operand is a FI, get the TargetFI Node
+    if (FrameIndexSDNode *FIN =
+            dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
+      Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
+    else
+      return false;
+
+    Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64);
+    return true;
+  }
+
+  return false;
+}
+
 SDNode *BPFDAGToDAGISel::Select(SDNode *Node) {
   unsigned Opcode = Node->getOpcode();
 
@@ -104,13 +130,6 @@ SDNode *BPFDAGToDAGISel::Select(SDNode *
   // tablegen selection should be handled here.
   switch (Opcode) {
   default: break;
-
-  case ISD::UNDEF: {
-    errs() << "BUG: "; Node->dump(CurDAG); errs() << '\n';
-    report_fatal_error("shouldn't see UNDEF during Select");
-    break;
-  }
-
   case ISD::INTRINSIC_W_CHAIN: {
     unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
     switch (IntNo) {

Modified: vendor/llvm/dist/lib/Target/BPF/BPFISelLowering.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/BPF/BPFISelLowering.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/BPF/BPFISelLowering.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -102,6 +102,7 @@ BPFTargetLowering::BPFTargetLowering(con
 
   setOperationAction(ISD::BR_CC, MVT::i64, Custom);
   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
+  setOperationAction(ISD::BRIND, MVT::Other, Expand);
   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
   setOperationAction(ISD::SETCC, MVT::i64, Expand);
   setOperationAction(ISD::SELECT, MVT::i64, Expand);
@@ -128,9 +129,6 @@ BPFTargetLowering::BPFTargetLowering(con
   setOperationAction(ISD::SUBC, MVT::i64, Expand);
   setOperationAction(ISD::SUBE, MVT::i64, Expand);
 
-  // no UNDEF allowed
-  setOperationAction(ISD::UNDEF, MVT::i64, Expand);
-
   setOperationAction(ISD::ROTR, MVT::i64, Expand);
   setOperationAction(ISD::ROTL, MVT::i64, Expand);
   setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);

Modified: vendor/llvm/dist/lib/Target/BPF/BPFInstrInfo.td
==============================================================================
--- vendor/llvm/dist/lib/Target/BPF/BPFInstrInfo.td	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/BPF/BPFInstrInfo.td	Fri Dec 25 14:25:49 2015	(r292726)
@@ -54,7 +54,8 @@ def i64immSExt32 : PatLeaf<(imm),
                 [{return isInt<32>(N->getSExtValue()); }]>;
 
 // Addressing modes.
-def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [frameindex], []>;
+def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
+def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
 
 // Address operands
 def MEMri : Operand<i64> {
@@ -260,6 +261,15 @@ def MOV_rr : MOV_RR<"mov">;
 def MOV_ri : MOV_RI<"mov">;
 }
 
+def FI_ri
+    : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
+               "lea\t$dst, $addr",
+               [(set i64:$dst, FIri:$addr)]> {
+  // This is a tentative instruction, and will be replaced
+  // with MOV_rr and ADD_ri in PEI phase
+}
+
+
 def LD_pseudo
     : InstBPF<(outs GPR:$dst), (ins i64imm:$pseudo, u64imm:$imm),
               "ld_pseudo\t$dst, $pseudo, $imm",

Modified: vendor/llvm/dist/lib/Target/BPF/BPFRegisterInfo.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/BPF/BPFRegisterInfo.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/BPF/BPFRegisterInfo.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -58,14 +58,13 @@ void BPFRegisterInfo::eliminateFrameInde
 
   unsigned FrameReg = getFrameRegister(MF);
   int FrameIndex = MI.getOperand(i).getIndex();
+  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
+  MachineBasicBlock &MBB = *MI.getParent();
 
   if (MI.getOpcode() == BPF::MOV_rr) {
-    const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
     int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
 
     MI.getOperand(i).ChangeToRegister(FrameReg, false);
-
-    MachineBasicBlock &MBB = *MI.getParent();
     unsigned reg = MI.getOperand(i - 1).getReg();
     BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
         .addReg(reg)
@@ -79,8 +78,24 @@ void BPFRegisterInfo::eliminateFrameInde
   if (!isInt<32>(Offset))
     llvm_unreachable("bug in frame offset");
 
-  MI.getOperand(i).ChangeToRegister(FrameReg, false);
-  MI.getOperand(i + 1).ChangeToImmediate(Offset);
+  if (MI.getOpcode() == BPF::FI_ri) {
+    // architecture does not really support FI_ri, replace it with
+    //    MOV_rr <target_reg>, frame_reg
+    //    ADD_ri <target_reg>, imm
+    unsigned reg = MI.getOperand(i - 1).getReg();
+
+    BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
+        .addReg(FrameReg);
+    BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
+        .addReg(reg)
+        .addImm(Offset);
+
+    // Remove FI_ri instruction
+    MI.eraseFromParent();
+  } else {
+    MI.getOperand(i).ChangeToRegister(FrameReg, false);
+    MI.getOperand(i + 1).ChangeToImmediate(Offset);
+  }
 }
 
 unsigned BPFRegisterInfo::getFrameRegister(const MachineFunction &MF) const {

Modified: vendor/llvm/dist/lib/Target/Mips/MipsISelLowering.h
==============================================================================
--- vendor/llvm/dist/lib/Target/Mips/MipsISelLowering.h	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/Mips/MipsISelLowering.h	Fri Dec 25 14:25:49 2015	(r292726)
@@ -269,6 +269,14 @@ namespace llvm {
     unsigned getRegisterByName(const char* RegName, EVT VT,
                                SelectionDAG &DAG) const override;
 
+    /// Returns true if a cast between SrcAS and DestAS is a noop.
+    bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
+      // Mips doesn't have any special address spaces so we just reserve
+      // the first 256 for software use (e.g. OpenCL) and treat casts
+      // between them as noops.
+      return SrcAS < 256 && DestAS < 256;
+    }
+
   protected:
     SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
 

Modified: vendor/llvm/dist/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/Mips/MipsSEISelDAGToDAG.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/Mips/MipsSEISelDAGToDAG.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -115,6 +115,11 @@ bool MipsSEDAGToDAGISel::replaceUsesWith
     if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
       continue;
 
+    // Also, we have to check that the register class of the operand
+    // contains the zero register.
+    if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
+      continue;
+
     MO.setReg(ZeroReg);
   }
 

Modified: vendor/llvm/dist/lib/Target/PowerPC/PPCAsmPrinter.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/PowerPC/PPCAsmPrinter.cpp	Fri Dec 25 13:03:18 2015	(r292725)
+++ vendor/llvm/dist/lib/Target/PowerPC/PPCAsmPrinter.cpp	Fri Dec 25 14:25:49 2015	(r292726)
@@ -947,11 +947,11 @@ void PPCAsmPrinter::EmitInstruction(cons
     return;
   }
   case PPC::ADDISdtprelHA:
-    // Transform: %Xd = ADDISdtprelHA %X3, <ga:@sym>
-    // Into:      %Xd = ADDIS8 %X3, sym@dtprel@ha
+    // Transform: %Xd = ADDISdtprelHA %Xs, <ga:@sym>
+    // Into:      %Xd = ADDIS8 %Xs, sym@dtprel@ha
   case PPC::ADDISdtprelHA32: {
-    // Transform: %Rd = ADDISdtprelHA32 %R3, <ga:@sym>
-    // Into:      %Rd = ADDIS %R3, sym@dtprel@ha
+    // Transform: %Rd = ADDISdtprelHA32 %Rs, <ga:@sym>
+    // Into:      %Rd = ADDIS %Rs, sym@dtprel@ha
     const MachineOperand &MO = MI->getOperand(2);
     const GlobalValue *GValue = MO.getGlobal();

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***



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