From owner-svn-src-all@FreeBSD.ORG Sat Mar 10 06:54:37 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id B8E791065676; Sat, 10 Mar 2012 06:54:37 +0000 (UTC) (envelope-from jmallett@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 8EB0A8FC0C; Sat, 10 Mar 2012 06:54:37 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q2A6sbna044400; Sat, 10 Mar 2012 06:54:37 GMT (envelope-from jmallett@svn.freebsd.org) Received: (from jmallett@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q2A6sb8s044396; Sat, 10 Mar 2012 06:54:37 GMT (envelope-from jmallett@svn.freebsd.org) Message-Id: <201203100654.q2A6sb8s044396@svn.freebsd.org> From: Juli Mallett Date: Sat, 10 Mar 2012 06:54:37 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r232770 - head/sys/mips/mips X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 10 Mar 2012 06:54:37 -0000 Author: jmallett Date: Sat Mar 10 06:54:37 2012 New Revision: 232770 URL: http://svn.freebsd.org/changeset/base/232770 Log: o) Remove some CPU_CNMIPS-related magical thinking about the status register's contents for user programs. o) Conditionalize the installation of an XTLB handler on ABI, not CPU family. Modified: head/sys/mips/mips/machdep.c head/sys/mips/mips/pm_machdep.c head/sys/mips/mips/vm_machdep.c Modified: head/sys/mips/mips/machdep.c ============================================================================== --- head/sys/mips/mips/machdep.c Sat Mar 10 06:45:21 2012 (r232769) +++ head/sys/mips/mips/machdep.c Sat Mar 10 06:54:37 2012 (r232770) @@ -347,8 +347,7 @@ mips_vector_init(void) bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC, MipsTLBMissEnd - MipsTLBMiss); -#if defined(CPU_CNMIPS) || defined(CPU_RMI) || defined(CPU_NLM) -/* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses */ +#ifdef __mips_n64 bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC, MipsTLBMissEnd - MipsTLBMiss); #endif Modified: head/sys/mips/mips/pm_machdep.c ============================================================================== --- head/sys/mips/mips/pm_machdep.c Sat Mar 10 06:45:21 2012 (r232769) +++ head/sys/mips/mips/pm_machdep.c Sat Mar 10 06:54:37 2012 (r232770) @@ -491,10 +491,6 @@ exec_setregs(struct thread *td, struct i #elif defined(__mips_n64) td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX; #endif -#ifdef CPU_CNMIPS - td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | - MIPS_SR_KX | MIPS_SR_SX; -#endif /* * FREEBSD_DEVELOPERS_FIXME: * Setup any other CPU-Specific registers (Not MIPS Standard) Modified: head/sys/mips/mips/vm_machdep.c ============================================================================== --- head/sys/mips/mips/vm_machdep.c Sat Mar 10 06:45:21 2012 (r232769) +++ head/sys/mips/mips/vm_machdep.c Sat Mar 10 06:54:37 2012 (r232770) @@ -406,12 +406,7 @@ cpu_set_upcall(struct thread *td, struct pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td->td_frame; /* Dont set IE bit in SR. sched lock release will take care of it */ pcb2->pcb_context[PCB_REG_SR] = mips_rd_status() & - (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_INT_MASK); - -#ifdef CPU_CNMIPS - pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_0_BIT | - MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX; -#endif + (MIPS_SR_PX | MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_INT_MASK); /* * FREEBSD_DEVELOPERS_FIXME: @@ -475,10 +470,6 @@ cpu_set_upcall_kse(struct thread *td, vo #elif defined(__mips_n64) td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX; #endif -#ifdef CPU_CNMIPS - tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS_SR_PX | MIPS_SR_UX | - MIPS_SR_KX; -#endif /* tf->sr |= (ALL_INT_MASK & idle_mask) | SR_INT_ENAB; */ /**XXX the above may now be wrong -- mips2 implements this as panic */ /*