From owner-freebsd-current@FreeBSD.ORG Thu Nov 8 10:23:04 2007 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 1FDA516A41A for ; Thu, 8 Nov 2007 10:23:04 +0000 (UTC) (envelope-from sos@deepcore.dk) Received: from spider.deepcore.dk (cpe.atm2-0-70484.0x50a6c9a6.abnxx16.customer.tele.dk [80.166.201.166]) by mx1.freebsd.org (Postfix) with ESMTP id 8FD2D13C48D for ; Thu, 8 Nov 2007 10:23:03 +0000 (UTC) (envelope-from sos@deepcore.dk) Received: from ws.local (ws.deepcore.dk [194.192.25.137]) by spider.deepcore.dk (8.13.8/8.13.8) with ESMTP id lA8AMtLr090569; Thu, 8 Nov 2007 11:22:55 +0100 (CET) (envelope-from sos@deepcore.dk) Message-ID: <4732E37F.9020707@deepcore.dk> Date: Thu, 08 Nov 2007 11:22:55 +0100 From: =?ISO-8859-1?Q?S=F8ren_Schmidt?= User-Agent: Thunderbird 2.0.0.6 (Macintosh/20070728) MIME-Version: 1.0 To: Alexander Sabourenkov References: <47326FB8.50602@fusiongol.com> <4732CEE3.3070003@lxnt.info> <4732DA32.3090601@deepcore.dk> <4732E18A.6040802@lxnt.info> In-Reply-To: <4732E18A.6040802@lxnt.info> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: quoted-printable Cc: Nathan Butcher , freebsd-current@freebsd.org Subject: Re: Remaining SATA (and other) issues X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Nov 2007 10:23:04 -0000 Alexander Sabourenkov wrote: > S=C3=B8ren Schmidt wrote: >> You cant remove this, ATA uses the 0x54 reg to store interrupts, its=20 >> a gen purpose reg on the promises, this initialization is neededed. > > Hmm. Cursory greps do not show writes there neither in vendor, nor in=20 > linux drivers. > I only found it in ata_piix.c from linux, as PIIX_IOCFG /* IDE I/O=20 > configuration register */. > > Thus I'm not sure it is really needed, but I leave that up to your=20 > expertise. As I said ATA (as in my driver) uses this promise general purpose=20 register to store interrupts into, it is very much needed. The reason is that on some promise chips the interrupts are reset on=20 read, so I can only read the status *once* but I need it several times. >> This part is wrong for older promise chips, as the port# is different.= >> I also have a hard time seeing that this couldd change anything since = >> the registers are reset etc "my way" on each interrupt. > > If that means ata_promise_mio_intr(), then no, it does not touch 0x60=20 > for PRSATA2, it touches 0x54 instead. Oh yes it does look for the "stat_reg" in ata_promise_mio_status() which = does the interrupt status getting etc... >> Besides you *do not* want to pass the other bits through, they shoudl = >> be masked off and always written as 0's. > > Why then vendor does pass them through? > Good question, their docs says nothing about it actually, I suppose this = is more a programming style question than anything else, anyhow it will=20 only change evt behavior until the first interrupt, then I'll write the=20 entire reg anyways :) -S=F8ren