Date: Wed, 4 Jan 2017 22:11:12 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r311315 - in vendor/llvm/dist: cmake cmake/modules include/llvm/ADT include/llvm/Analysis include/llvm/CodeGen include/llvm/DebugInfo/DWARF include/llvm/IR include/llvm/Support lib/Anal... Message-ID: <201701042211.v04MBCxg018751@repo.freebsd.org>
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Author: dim Date: Wed Jan 4 22:11:11 2017 New Revision: 311315 URL: https://svnweb.freebsd.org/changeset/base/311315 Log: Vendor import of llvm trunk r291012: https://llvm.org/svn/llvm-project/llvm/trunk@291012 Added: vendor/llvm/dist/test/Analysis/RegionInfo/bad_node_traversal.ll vendor/llvm/dist/test/CodeGen/AArch64/store_merge_pair_offset.ll vendor/llvm/dist/test/CodeGen/AMDGPU/amdgcn.sendmsg-m0.ll vendor/llvm/dist/test/CodeGen/AMDGPU/amdgcn.sendmsg.ll vendor/llvm/dist/test/CodeGen/PowerPC/ppc64-blnop.ll vendor/llvm/dist/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll vendor/llvm/dist/test/CodeGen/X86/frame-lowering-debug-intrinsic-2.ll vendor/llvm/dist/test/DebugInfo/Generic/simplifycfg_sink_last_inst.ll vendor/llvm/dist/test/DebugInfo/X86/dbg-value-frame-index.ll vendor/llvm/dist/test/Transforms/InstCombine/fma.ll vendor/llvm/dist/test/Transforms/InstCombine/sink-zext.ll vendor/llvm/dist/test/Transforms/NewGVN/equivalent-phi.ll vendor/llvm/dist/test/Transforms/NewGVN/pr31483.ll vendor/llvm/dist/test/Transforms/PartiallyInlineLibCalls/X86/ vendor/llvm/dist/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll vendor/llvm/dist/test/Transforms/PartiallyInlineLibCalls/X86/lit.local.cfg Deleted: vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.SI.sendmsg-m0.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.SI.sendmsg.ll Modified: vendor/llvm/dist/cmake/config-ix.cmake vendor/llvm/dist/cmake/modules/CheckCompilerVersion.cmake vendor/llvm/dist/include/llvm/ADT/IntrusiveRefCntPtr.h vendor/llvm/dist/include/llvm/ADT/PriorityWorklist.h vendor/llvm/dist/include/llvm/Analysis/Loads.h vendor/llvm/dist/include/llvm/CodeGen/AsmPrinter.h vendor/llvm/dist/include/llvm/CodeGen/MachineDominators.h vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDebugLine.h vendor/llvm/dist/include/llvm/IR/IntrinsicsAMDGPU.td vendor/llvm/dist/include/llvm/IR/IntrinsicsX86.td vendor/llvm/dist/include/llvm/Support/FileSystem.h vendor/llvm/dist/include/llvm/Support/YAMLTraits.h vendor/llvm/dist/lib/Analysis/ValueTracking.cpp vendor/llvm/dist/lib/Bitcode/Reader/MetadataLoader.cpp vendor/llvm/dist/lib/CodeGen/Analysis.cpp vendor/llvm/dist/lib/CodeGen/AsmPrinter/AsmPrinter.cpp vendor/llvm/dist/lib/CodeGen/InlineSpiller.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp vendor/llvm/dist/lib/ExecutionEngine/OProfileJIT/OProfileJITEventListener.cpp vendor/llvm/dist/lib/Fuzzer/FuzzerTracePC.cpp vendor/llvm/dist/lib/IR/AutoUpgrade.cpp vendor/llvm/dist/lib/LTO/LTO.cpp vendor/llvm/dist/lib/Support/APFloat.cpp vendor/llvm/dist/lib/Support/Host.cpp vendor/llvm/dist/lib/Support/NativeFormatting.cpp vendor/llvm/dist/lib/Support/YAMLTraits.cpp vendor/llvm/dist/lib/TableGen/StringMatcher.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64.td vendor/llvm/dist/lib/Target/AArch64/AArch64AsmPrinter.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUISelLowering.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUISelLowering.h vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUInstrInfo.td vendor/llvm/dist/lib/Target/AMDGPU/SIISelLowering.cpp vendor/llvm/dist/lib/Target/AMDGPU/SIInsertWaits.cpp vendor/llvm/dist/lib/Target/AMDGPU/SOPInstructions.td vendor/llvm/dist/lib/Target/ARM/ARMAsmPrinter.cpp vendor/llvm/dist/lib/Target/ARM/ARMAsmPrinter.h vendor/llvm/dist/lib/Target/ARM/ARMMCInstLower.cpp vendor/llvm/dist/lib/Target/Hexagon/BitTracker.cpp vendor/llvm/dist/lib/Target/Hexagon/BitTracker.h vendor/llvm/dist/lib/Target/Hexagon/HexagonBitTracker.cpp vendor/llvm/dist/lib/Target/Hexagon/HexagonBitTracker.h vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrInfo.cpp vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrInfo.h vendor/llvm/dist/lib/Target/Hexagon/HexagonMachineFunctionInfo.h vendor/llvm/dist/lib/Target/Hexagon/HexagonTargetObjectFile.cpp vendor/llvm/dist/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp vendor/llvm/dist/lib/Target/Hexagon/RDFCopy.h vendor/llvm/dist/lib/Target/Hexagon/RDFGraph.cpp vendor/llvm/dist/lib/Target/Hexagon/RDFGraph.h vendor/llvm/dist/lib/Target/Mips/MipsSEISelDAGToDAG.cpp vendor/llvm/dist/lib/Target/Mips/MipsSEISelDAGToDAG.h vendor/llvm/dist/lib/Target/PowerPC/PPCISelLowering.cpp vendor/llvm/dist/lib/Target/X86/X86AsmPrinter.cpp vendor/llvm/dist/lib/Target/X86/X86FrameLowering.cpp vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td vendor/llvm/dist/lib/Target/X86/X86InstrSSE.td vendor/llvm/dist/lib/Target/X86/X86InstrTablesInfo.h vendor/llvm/dist/lib/Target/X86/X86IntrinsicsInfo.h vendor/llvm/dist/lib/Target/X86/X86MCInstLower.cpp vendor/llvm/dist/lib/Target/X86/X86TargetTransformInfo.cpp vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineAddSub.cpp vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineCalls.cpp vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineShifts.cpp vendor/llvm/dist/lib/Transforms/Scalar/EarlyCSE.cpp vendor/llvm/dist/lib/Transforms/Scalar/NewGVN.cpp vendor/llvm/dist/lib/Transforms/Utils/InlineFunction.cpp vendor/llvm/dist/lib/Transforms/Utils/LoopUnrollPeel.cpp vendor/llvm/dist/lib/Transforms/Utils/SimplifyCFG.cpp vendor/llvm/dist/runtimes/CMakeLists.txt vendor/llvm/dist/test/Analysis/CostModel/X86/alternate-shuffle-cost.ll vendor/llvm/dist/test/Bitcode/DIGlobalVariableExpression.ll vendor/llvm/dist/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll vendor/llvm/dist/test/CodeGen/PowerPC/ppc64-sibcall.ll vendor/llvm/dist/test/CodeGen/SPARC/soft-float.ll vendor/llvm/dist/test/CodeGen/X86/MergeConsecutiveStores.ll vendor/llvm/dist/test/CodeGen/X86/avx2-vbroadcast.ll vendor/llvm/dist/test/CodeGen/X86/avx512-any_extend_load.ll vendor/llvm/dist/test/CodeGen/X86/avx512-extract-subvector.ll vendor/llvm/dist/test/CodeGen/X86/avx512-insert-extract.ll vendor/llvm/dist/test/CodeGen/X86/avx512-intrinsics-upgrade.ll vendor/llvm/dist/test/CodeGen/X86/avx512-intrinsics.ll vendor/llvm/dist/test/CodeGen/X86/avx512-skx-insert-subvec.ll vendor/llvm/dist/test/CodeGen/X86/avx512-vbroadcasti128.ll vendor/llvm/dist/test/CodeGen/X86/avx512bwvl-intrinsics.ll vendor/llvm/dist/test/CodeGen/X86/avx512dq-intrinsics.ll vendor/llvm/dist/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll vendor/llvm/dist/test/CodeGen/X86/avx512dqvl-intrinsics.ll vendor/llvm/dist/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll vendor/llvm/dist/test/CodeGen/X86/avx512vl-intrinsics.ll vendor/llvm/dist/test/CodeGen/X86/frame-lowering-debug-intrinsic.ll vendor/llvm/dist/test/CodeGen/X86/i64-to-float.ll vendor/llvm/dist/test/CodeGen/X86/masked_memop.ll vendor/llvm/dist/test/CodeGen/X86/stack-folding-fp-avx512vl.ll vendor/llvm/dist/test/CodeGen/X86/stack-folding-int-avx512vl.ll vendor/llvm/dist/test/CodeGen/X86/subvector-broadcast.ll vendor/llvm/dist/test/CodeGen/X86/vec_fp_to_int.ll vendor/llvm/dist/test/CodeGen/X86/vec_int_to_fp.ll vendor/llvm/dist/test/CodeGen/X86/vector-half-conversions.ll vendor/llvm/dist/test/CodeGen/X86/vector-lzcnt-256.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-256-v16.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-256-v32.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-256-v4.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-256-v8.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-512-v16.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-512-v8.ll vendor/llvm/dist/test/CodeGen/X86/vector-trunc-math.ll vendor/llvm/dist/test/CodeGen/X86/vector-trunc.ll vendor/llvm/dist/test/MC/ARM/coff-relocations.s vendor/llvm/dist/test/ThinLTO/X86/drop-debug-info.ll vendor/llvm/dist/test/Transforms/Inline/inline-invoke-tail.ll vendor/llvm/dist/test/Transforms/InstCombine/add.ll vendor/llvm/dist/test/Transforms/InstCombine/assume.ll vendor/llvm/dist/test/Transforms/InstCombine/fabs.ll vendor/llvm/dist/test/Transforms/InstCombine/rem.ll vendor/llvm/dist/test/Transforms/InstCombine/shift.ll vendor/llvm/dist/test/Transforms/LoopIdiom/basic.ll vendor/llvm/dist/test/Transforms/LoopUnroll/peel-loop-pgo.ll vendor/llvm/dist/test/Transforms/SLPVectorizer/X86/horizontal-list.ll vendor/llvm/dist/test/tools/gold/X86/Inputs/thinlto.ll vendor/llvm/dist/test/tools/gold/X86/Inputs/thinlto_archive1.ll vendor/llvm/dist/test/tools/gold/X86/Inputs/thinlto_archive2.ll vendor/llvm/dist/test/tools/gold/X86/comdat.ll vendor/llvm/dist/test/tools/gold/X86/opt-level.ll vendor/llvm/dist/test/tools/gold/X86/pr25907.ll vendor/llvm/dist/test/tools/gold/X86/stats.ll vendor/llvm/dist/test/tools/gold/X86/strip_names.ll vendor/llvm/dist/test/tools/gold/X86/thinlto.ll vendor/llvm/dist/test/tools/gold/X86/thinlto_afdo.ll vendor/llvm/dist/test/tools/gold/X86/thinlto_archive.ll vendor/llvm/dist/test/tools/gold/X86/type-merge2.ll vendor/llvm/dist/test/tools/gold/X86/visibility.ll vendor/llvm/dist/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp vendor/llvm/dist/tools/llvm-link/CMakeLists.txt vendor/llvm/dist/tools/llvm-link/LLVMBuild.txt vendor/llvm/dist/tools/llvm-link/llvm-link.cpp vendor/llvm/dist/unittests/ADT/PriorityWorklistTest.cpp vendor/llvm/dist/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp vendor/llvm/dist/unittests/Support/YAMLIOTest.cpp Modified: vendor/llvm/dist/cmake/config-ix.cmake ============================================================================== --- vendor/llvm/dist/cmake/config-ix.cmake Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/cmake/config-ix.cmake Wed Jan 4 22:11:11 2017 (r311315) @@ -457,6 +457,13 @@ if( MSVC ) if(LLVM_ENABLE_DIA_SDK AND NOT HAVE_DIA_SDK) message(FATAL_ERROR "DIA SDK not found. If you have both VS 2012 and 2013 installed, you may need to uninstall the former and re-install the latter afterwards.") endif() + + # Normalize to 0/1 for lit.site.cfg + if(LLVM_ENABLE_DIA_SDK) + set(LLVM_ENABLE_DIA_SDK 1) + else() + set(LLVM_ENABLE_DIA_SDK 0) + endif() else() set(LLVM_ENABLE_DIA_SDK 0) endif( MSVC ) Modified: vendor/llvm/dist/cmake/modules/CheckCompilerVersion.cmake ============================================================================== --- vendor/llvm/dist/cmake/modules/CheckCompilerVersion.cmake Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/cmake/modules/CheckCompilerVersion.cmake Wed Jan 4 22:11:11 2017 (r311315) @@ -43,8 +43,8 @@ int main() { return (float)x; }" elseif(CMAKE_CXX_COMPILER_ID MATCHES "MSVC") if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS 19.0) message(FATAL_ERROR "Host Visual Studio must be at least 2015") - elseif(CMAKE_CXX_COMPILER_VERSION VERSION_LESS 19.00.24215.1) - message(WARNING "Host Visual Studio should at least be 2015 Update 3 (MSVC 19.00.24215.1)" + elseif(CMAKE_CXX_COMPILER_VERSION VERSION_LESS 19.00.24213.1) + message(WARNING "Host Visual Studio should at least be 2015 Update 3 (MSVC 19.00.24213.1)" " due to miscompiles from earlier versions") endif() endif() Modified: vendor/llvm/dist/include/llvm/ADT/IntrusiveRefCntPtr.h ============================================================================== --- vendor/llvm/dist/include/llvm/ADT/IntrusiveRefCntPtr.h Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/include/llvm/ADT/IntrusiveRefCntPtr.h Wed Jan 4 22:11:11 2017 (r311315) @@ -21,8 +21,8 @@ // class MyClass : public RefCountedBase<MyClass> {}; // // void foo() { -// // Objects that inherit from RefCountedBase should always be instantiated -// // on the heap, never on the stack. +// // Constructing an IntrusiveRefCntPtr increases the pointee's refcount by +// // 1 (from 0 in this case). // IntrusiveRefCntPtr<MyClass> Ptr1(new MyClass()); // // // Copying an IntrusiveRefCntPtr increases the pointee's refcount by 1. @@ -68,9 +68,6 @@ namespace llvm { /// calls to Release() and Retain(), which increment and decrement the object's /// refcount, respectively. When a Release() call decrements the refcount to 0, /// the object deletes itself. -/// -/// Objects that inherit from RefCountedBase should always be allocated with -/// operator new. template <class Derived> class RefCountedBase { mutable unsigned RefCount = 0; Modified: vendor/llvm/dist/include/llvm/ADT/PriorityWorklist.h ============================================================================== --- vendor/llvm/dist/include/llvm/ADT/PriorityWorklist.h Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/include/llvm/ADT/PriorityWorklist.h Wed Jan 4 22:11:11 2017 (r311315) @@ -18,6 +18,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/Sequence.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/Compiler.h" #include <algorithm> @@ -107,6 +108,39 @@ public: return false; } + /// Insert a sequence of new elements into the PriorityWorklist. + template <typename SequenceT> + typename std::enable_if<!std::is_convertible<SequenceT, T>::value>::type + insert(SequenceT &&Input) { + if (std::begin(Input) == std::end(Input)) + // Nothing to do for an empty input sequence. + return; + + // First pull the input sequence into the vector as a bulk append + // operation. + ptrdiff_t StartIndex = V.size(); + V.insert(V.end(), std::begin(Input), std::end(Input)); + // Now walk backwards fixing up the index map and deleting any duplicates. + for (ptrdiff_t i = V.size() - 1; i >= StartIndex; --i) { + auto InsertResult = M.insert({V[i], i}); + if (InsertResult.second) + continue; + + // If the existing index is before this insert's start, nuke that one and + // move it up. + ptrdiff_t &Index = InsertResult.first->second; + if (Index < StartIndex) { + V[Index] = T(); + Index = i; + continue; + } + + // Otherwise the existing one comes first so just clear out the value in + // this slot. + V[i] = T(); + } + } + /// Remove the last element of the PriorityWorklist. void pop_back() { assert(!empty() && "Cannot remove an element when empty!"); @@ -169,6 +203,11 @@ public: return true; } + /// Reverse the items in the PriorityWorklist. + /// + /// This does an in-place reversal. Other kinds of reverse aren't easy to + /// support in the face of the worklist semantics. + /// Completely clear the PriorityWorklist void clear() { M.clear(); Modified: vendor/llvm/dist/include/llvm/Analysis/Loads.h ============================================================================== --- vendor/llvm/dist/include/llvm/Analysis/Loads.h Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/include/llvm/Analysis/Loads.h Wed Jan 4 22:11:11 2017 (r311315) @@ -23,10 +23,9 @@ namespace llvm { class DataLayout; class MDNode; -/// isDereferenceablePointer - Return true if this is always a dereferenceable -/// pointer. If the context instruction is specified perform context-sensitive -/// analysis and return true if the pointer is dereferenceable at the -/// specified instruction. +/// Return true if this is always a dereferenceable pointer. If the context +/// instruction is specified perform context-sensitive analysis and return true +/// if the pointer is dereferenceable at the specified instruction. bool isDereferenceablePointer(const Value *V, const DataLayout &DL, const Instruction *CtxI = nullptr, const DominatorTree *DT = nullptr); @@ -40,8 +39,7 @@ bool isDereferenceableAndAlignedPointer( const Instruction *CtxI = nullptr, const DominatorTree *DT = nullptr); -/// isSafeToLoadUnconditionally - Return true if we know that executing a load -/// from this value cannot trap. +/// Return true if we know that executing a load from this value cannot trap. /// /// If DT and ScanFrom are specified this method performs context-sensitive /// analysis and returns true if it is safe to load immediately before ScanFrom. @@ -54,12 +52,12 @@ bool isSafeToLoadUnconditionally(Value * Instruction *ScanFrom = nullptr, const DominatorTree *DT = nullptr); -/// DefMaxInstsToScan - the default number of maximum instructions -/// to scan in the block, used by FindAvailableLoadedValue(). +/// The default number of maximum instructions to scan in the block, used by +/// FindAvailableLoadedValue(). extern cl::opt<unsigned> DefMaxInstsToScan; -/// \brief Scan backwards to see if we have the value of the given load -/// available locally within a small number of instructions. +/// Scan backwards to see if we have the value of the given load available +/// locally within a small number of instructions. /// /// You can use this function to scan across multiple blocks: after you call /// this function, if ScanFrom points at the beginning of the block, it's safe Modified: vendor/llvm/dist/include/llvm/CodeGen/AsmPrinter.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/AsmPrinter.h Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/include/llvm/CodeGen/AsmPrinter.h Wed Jan 4 22:11:11 2017 (r311315) @@ -208,6 +208,8 @@ public: SledKind Kind; bool AlwaysInstrument; const class Function *Fn; + + void emit(int, MCStreamer *, const MCSymbol *) const; }; // All the sleds to be emitted. @@ -216,6 +218,9 @@ public: // Helper function to record a given XRay sled. void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind); + /// Emit a table with all XRay instrumentation points. + void emitXRayTable(); + //===------------------------------------------------------------------===// // MachineFunctionPass Implementation. //===------------------------------------------------------------------===// Modified: vendor/llvm/dist/include/llvm/CodeGen/MachineDominators.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/MachineDominators.h Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/include/llvm/CodeGen/MachineDominators.h Wed Jan 4 22:11:11 2017 (r311315) @@ -59,6 +59,9 @@ class MachineDominatorTree : public Mach /// such as BB == elt.NewBB. mutable SmallSet<MachineBasicBlock *, 32> NewBBs; + /// The DominatorTreeBase that is used to compute a normal dominator tree + DominatorTreeBase<MachineBasicBlock>* DT; + /// \brief Apply all the recorded critical edges to the DT. /// This updates the underlying DT information in a way that uses /// the fast query path of DT as much as possible. @@ -68,7 +71,6 @@ class MachineDominatorTree : public Mach public: static char ID; // Pass ID, replacement for typeid - DominatorTreeBase<MachineBasicBlock>* DT; MachineDominatorTree(); Modified: vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDebugLine.h ============================================================================== --- vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDebugLine.h Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/include/llvm/DebugInfo/DWARF/DWARFDebugLine.h Wed Jan 4 22:11:11 2017 (r311315) @@ -116,12 +116,12 @@ public: // An unsigned integer indicating the identity of the source file // corresponding to a machine instruction. uint16_t File; - // An unsigned integer whose value encodes the applicable instruction set - // architecture for the current instruction. - uint8_t Isa; // An unsigned integer representing the DWARF path discriminator value // for this location. uint32_t Discriminator; + // An unsigned integer whose value encodes the applicable instruction set + // architecture for the current instruction. + uint8_t Isa; // A boolean indicating that the current instruction is the beginning of a // statement. uint8_t IsStmt:1, Modified: vendor/llvm/dist/include/llvm/IR/IntrinsicsAMDGPU.td ============================================================================== --- vendor/llvm/dist/include/llvm/IR/IntrinsicsAMDGPU.td Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/include/llvm/IR/IntrinsicsAMDGPU.td Wed Jan 4 22:11:11 2017 (r311315) @@ -104,6 +104,13 @@ def int_amdgcn_dispatch_id : // Instruction Intrinsics //===----------------------------------------------------------------------===// +// The first parameter is s_sendmsg immediate (i16), +// the second one is copied to m0 +def int_amdgcn_s_sendmsg : GCCBuiltin<"__builtin_amdgcn_s_sendmsg">, + Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], []>; +def int_amdgcn_s_sendmsghalt : GCCBuiltin<"__builtin_amdgcn_s_sendmsghalt">, + Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], []>; + def int_amdgcn_s_barrier : GCCBuiltin<"__builtin_amdgcn_s_barrier">, Intrinsic<[], [], [IntrConvergent]>; Modified: vendor/llvm/dist/include/llvm/IR/IntrinsicsX86.td ============================================================================== --- vendor/llvm/dist/include/llvm/IR/IntrinsicsX86.td Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/include/llvm/IR/IntrinsicsX86.td Wed Jan 4 22:11:11 2017 (r311315) @@ -2063,130 +2063,6 @@ let TargetPrefix = "x86" in { // All in llvm_v4i64_ty, llvm_i8_ty], [IntrNoMem]>; } -// Vector extract and insert -let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". - def int_x86_avx512_mask_vextractf32x4_512 : - GCCBuiltin<"__builtin_ia32_extractf32x4_mask">, - Intrinsic<[llvm_v4f32_ty], [llvm_v16f32_ty, llvm_i32_ty, - llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_vextracti32x4_512 : - GCCBuiltin<"__builtin_ia32_extracti32x4_mask">, - Intrinsic<[llvm_v4i32_ty], [llvm_v16i32_ty, llvm_i32_ty, - llvm_v4i32_ty, llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_vextractf32x4_256 : - GCCBuiltin<"__builtin_ia32_extractf32x4_256_mask">, - Intrinsic<[llvm_v4f32_ty], [llvm_v8f32_ty, llvm_i32_ty, - llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_vextracti32x4_256 : - GCCBuiltin<"__builtin_ia32_extracti32x4_256_mask">, - Intrinsic<[llvm_v4i32_ty], [llvm_v8i32_ty, llvm_i32_ty, - llvm_v4i32_ty, llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_vextractf64x2_256 : - GCCBuiltin<"__builtin_ia32_extractf64x2_256_mask">, - Intrinsic<[llvm_v2f64_ty], [llvm_v4f64_ty, llvm_i32_ty, - llvm_v2f64_ty, llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_vextracti64x2_256 : - GCCBuiltin<"__builtin_ia32_extracti64x2_256_mask">, - Intrinsic<[llvm_v2i64_ty], [llvm_v4i64_ty, llvm_i32_ty, - llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_vextractf64x2_512 : - GCCBuiltin<"__builtin_ia32_extractf64x2_512_mask">, - Intrinsic<[llvm_v2f64_ty], [llvm_v8f64_ty, llvm_i32_ty, - llvm_v2f64_ty, llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_vextracti64x2_512 : - GCCBuiltin<"__builtin_ia32_extracti64x2_512_mask">, - Intrinsic<[llvm_v2i64_ty], [llvm_v8i64_ty, llvm_i32_ty, - llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_vextractf32x8_512 : - GCCBuiltin<"__builtin_ia32_extractf32x8_mask">, - Intrinsic<[llvm_v8f32_ty], [llvm_v16f32_ty, llvm_i32_ty, - llvm_v8f32_ty, llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_vextracti32x8_512 : - GCCBuiltin<"__builtin_ia32_extracti32x8_mask">, - Intrinsic<[llvm_v8i32_ty],[llvm_v16i32_ty, llvm_i32_ty, - llvm_v8i32_ty, llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_vextractf64x4_512 : - GCCBuiltin<"__builtin_ia32_extractf64x4_mask">, - Intrinsic<[llvm_v4f64_ty], [llvm_v8f64_ty, llvm_i32_ty, - llvm_v4f64_ty, llvm_i8_ty], [IntrNoMem]>; - def int_x86_avx512_mask_vextracti64x4_512 : - GCCBuiltin<"__builtin_ia32_extracti64x4_mask">, - Intrinsic<[llvm_v4i64_ty], [llvm_v8i64_ty, llvm_i32_ty, - llvm_v4i64_ty, llvm_i8_ty], [IntrNoMem]>; - - def int_x86_avx512_mask_insertf32x4_256 : - GCCBuiltin<"__builtin_ia32_insertf32x4_256_mask">, - Intrinsic<[llvm_v8f32_ty], - [llvm_v8f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_v8f32_ty, llvm_i8_ty], - [IntrNoMem]>; - - def int_x86_avx512_mask_insertf32x4_512 : - GCCBuiltin<"__builtin_ia32_insertf32x4_mask">, - Intrinsic<[llvm_v16f32_ty], - [llvm_v16f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_v16f32_ty, llvm_i16_ty], - [IntrNoMem]>; - - def int_x86_avx512_mask_insertf32x8_512 : - GCCBuiltin<"__builtin_ia32_insertf32x8_mask">, - Intrinsic<[llvm_v16f32_ty], - [llvm_v16f32_ty, llvm_v8f32_ty, llvm_i32_ty, llvm_v16f32_ty, llvm_i16_ty], - [IntrNoMem]>; - - def int_x86_avx512_mask_insertf64x2_256 : - GCCBuiltin<"__builtin_ia32_insertf64x2_256_mask">, - Intrinsic<[llvm_v4f64_ty], - [llvm_v4f64_ty, llvm_v2f64_ty, llvm_i32_ty, llvm_v4f64_ty, llvm_i8_ty], - [IntrNoMem]>; - - def int_x86_avx512_mask_insertf64x2_512 : - GCCBuiltin<"__builtin_ia32_insertf64x2_512_mask">, - Intrinsic<[llvm_v8f64_ty], - [llvm_v8f64_ty, llvm_v2f64_ty, llvm_i32_ty, llvm_v8f64_ty, llvm_i8_ty], - [IntrNoMem]>; - - def int_x86_avx512_mask_insertf64x4_512 : - GCCBuiltin<"__builtin_ia32_insertf64x4_mask">, - Intrinsic<[llvm_v8f64_ty], - [llvm_v8f64_ty, llvm_v4f64_ty, llvm_i32_ty, llvm_v8f64_ty, llvm_i8_ty], - [IntrNoMem]>; - - def int_x86_avx512_mask_inserti32x4_256 : - GCCBuiltin<"__builtin_ia32_inserti32x4_256_mask">, - Intrinsic<[llvm_v8i32_ty], - [llvm_v8i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_v8i32_ty, llvm_i8_ty], - [IntrNoMem]>; - - def int_x86_avx512_mask_inserti32x4_512 : - GCCBuiltin<"__builtin_ia32_inserti32x4_mask">, - Intrinsic<[llvm_v16i32_ty], - [llvm_v16i32_ty, llvm_v4i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_i16_ty], - [IntrNoMem]>; - - def int_x86_avx512_mask_inserti32x8_512 : - GCCBuiltin<"__builtin_ia32_inserti32x8_mask">, - Intrinsic<[llvm_v16i32_ty], - [llvm_v16i32_ty, llvm_v8i32_ty, llvm_i32_ty, llvm_v16i32_ty, llvm_i16_ty], - [IntrNoMem]>; - - def int_x86_avx512_mask_inserti64x2_256 : - GCCBuiltin<"__builtin_ia32_inserti64x2_256_mask">, - Intrinsic<[llvm_v4i64_ty], - [llvm_v4i64_ty, llvm_v2i64_ty, llvm_i32_ty, llvm_v4i64_ty, llvm_i8_ty], - [IntrNoMem]>; - - def int_x86_avx512_mask_inserti64x2_512 : - GCCBuiltin<"__builtin_ia32_inserti64x2_512_mask">, - Intrinsic<[llvm_v8i64_ty], - [llvm_v8i64_ty, llvm_v2i64_ty, llvm_i32_ty, llvm_v8i64_ty, llvm_i8_ty], - [IntrNoMem]>; - - def int_x86_avx512_mask_inserti64x4_512 : - GCCBuiltin<"__builtin_ia32_inserti64x4_mask">, - Intrinsic<[llvm_v8i64_ty], - [llvm_v8i64_ty, llvm_v4i64_ty, llvm_i32_ty, llvm_v8i64_ty, llvm_i8_ty], - [IntrNoMem]>; -} - // Conditional load ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_avx2_maskload_d : GCCBuiltin<"__builtin_ia32_maskloadd">, Modified: vendor/llvm/dist/include/llvm/Support/FileSystem.h ============================================================================== --- vendor/llvm/dist/include/llvm/Support/FileSystem.h Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/include/llvm/Support/FileSystem.h Wed Jan 4 22:11:11 2017 (r311315) @@ -769,17 +769,13 @@ namespace detail { std::error_code directory_iterator_increment(DirIterState &); std::error_code directory_iterator_destruct(DirIterState &); - /// DirIterState - Keeps state for the directory_iterator. It is reference - /// counted in order to preserve InputIterator semantics on copy. - struct DirIterState : public RefCountedBase<DirIterState> { - DirIterState() - : IterationHandle(0) {} - + /// Keeps state for the directory_iterator. + struct DirIterState { ~DirIterState() { directory_iterator_destruct(*this); } - intptr_t IterationHandle; + intptr_t IterationHandle = 0; directory_entry CurrentEntry; }; } // end namespace detail @@ -788,23 +784,23 @@ namespace detail { /// operator++ because we need an error_code. If it's really needed we can make /// it call report_fatal_error on error. class directory_iterator { - IntrusiveRefCntPtr<detail::DirIterState> State; + std::shared_ptr<detail::DirIterState> State; public: explicit directory_iterator(const Twine &path, std::error_code &ec) { - State = new detail::DirIterState; + State = std::make_shared<detail::DirIterState>(); SmallString<128> path_storage; ec = detail::directory_iterator_construct(*State, path.toStringRef(path_storage)); } explicit directory_iterator(const directory_entry &de, std::error_code &ec) { - State = new detail::DirIterState; + State = std::make_shared<detail::DirIterState>(); ec = detail::directory_iterator_construct(*State, de.path()); } /// Construct end iterator. - directory_iterator() : State(nullptr) {} + directory_iterator() = default; // No operator++ because we need error_code. directory_iterator &increment(std::error_code &ec) { Modified: vendor/llvm/dist/include/llvm/Support/YAMLTraits.h ============================================================================== --- vendor/llvm/dist/include/llvm/Support/YAMLTraits.h Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/include/llvm/Support/YAMLTraits.h Wed Jan 4 22:11:11 2017 (r311315) @@ -209,6 +209,15 @@ struct DocumentListTraits { // static T::value_type& element(IO &io, T &seq, size_t index); }; +/// This class should be specialized by any type that needs to be converted +/// to/from a YAML mapping in the case where the names of the keys are not known +/// in advance, e.g. a string map. +template <typename T> +struct CustomMappingTraits { + // static void inputOne(IO &io, StringRef key, T &elem); + // static void output(IO &io, T &elem); +}; + // Only used for better diagnostics of missing traits template <typename T> struct MissingTrait; @@ -358,6 +367,23 @@ public: static bool const value = (sizeof(test<SequenceTraits<T>>(nullptr)) == 1); }; +// Test if CustomMappingTraits<T> is defined on type T. +template <class T> +struct has_CustomMappingTraits +{ + typedef void (*Signature_input)(IO &io, StringRef key, T &v); + + template <typename U> + static char test(SameType<Signature_input, &U::inputOne>*); + + template <typename U> + static double test(...); + +public: + static bool const value = + (sizeof(test<CustomMappingTraits<T>>(nullptr)) == 1); +}; + // has_FlowTraits<int> will cause an error with some compilers because // it subclasses int. Using this wrapper only instantiates the // real has_FlowTraits only if the template type is a class. @@ -493,6 +519,7 @@ struct missingTraits !has_BlockScalarTraits<T>::value && !has_MappingTraits<T, Context>::value && !has_SequenceTraits<T>::value && + !has_CustomMappingTraits<T>::value && !has_DocumentListTraits<T>::value> {}; template <typename T, typename Context> @@ -531,6 +558,7 @@ public: virtual void endMapping() = 0; virtual bool preflightKey(const char*, bool, bool, bool &, void *&) = 0; virtual void postflightKey(void*) = 0; + virtual std::vector<StringRef> keys() = 0; virtual void beginFlowMapping() = 0; virtual void endFlowMapping() = 0; @@ -819,6 +847,21 @@ yamlize(IO &io, T &Val, bool, Context &C } template <typename T> +typename std::enable_if<has_CustomMappingTraits<T>::value, void>::type +yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { + if ( io.outputting() ) { + io.beginMapping(); + CustomMappingTraits<T>::output(io, Val); + io.endMapping(); + } else { + io.beginMapping(); + for (StringRef key : io.keys()) + CustomMappingTraits<T>::inputOne(io, key, Val); + io.endMapping(); + } +} + +template <typename T> typename std::enable_if<missingTraits<T, EmptyContext>::value, void>::type yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { char missing_yaml_trait_for_type[sizeof(MissingTrait<T>)]; @@ -1074,6 +1117,7 @@ private: void endMapping() override; bool preflightKey(const char *, bool, bool, bool &, void *&) override; void postflightKey(void *) override; + std::vector<StringRef> keys() override; void beginFlowMapping() override; void endFlowMapping() override; unsigned beginSequence() override; @@ -1154,10 +1198,8 @@ private: typedef llvm::StringMap<std::unique_ptr<HNode>> NameToNode; - bool isValidKey(StringRef key); - NameToNode Mapping; - llvm::SmallVector<const char*, 6> ValidKeys; + llvm::SmallVector<std::string, 6> ValidKeys; }; class SequenceHNode : public HNode { @@ -1215,6 +1257,7 @@ public: void endMapping() override; bool preflightKey(const char *key, bool, bool, bool &, void *&) override; void postflightKey(void *) override; + std::vector<StringRef> keys() override; void beginFlowMapping() override; void endFlowMapping() override; unsigned beginSequence() override; @@ -1384,6 +1427,17 @@ operator>>(Input &In, T &Val) { return In; } +// Define non-member operator>> so that Input can stream in a string map. +template <typename T> +inline +typename std::enable_if<has_CustomMappingTraits<T>::value, Input &>::type +operator>>(Input &In, T &Val) { + EmptyContext Ctx; + if (In.setCurrentDocument()) + yamlize(In, Val, true, Ctx); + return In; +} + // Provide better error message about types missing a trait specialization template <typename T> inline typename std::enable_if<missingTraits<T, EmptyContext>::value, @@ -1457,6 +1511,21 @@ operator<<(Output &Out, T &Val) { return Out; } +// Define non-member operator<< so that Output can stream out a string map. +template <typename T> +inline +typename std::enable_if<has_CustomMappingTraits<T>::value, Output &>::type +operator<<(Output &Out, T &Val) { + EmptyContext Ctx; + Out.beginDocuments(); + if (Out.preflightDocument(0)) { + yamlize(Out, Val, true, Ctx); + Out.postflightDocument(); + } + Out.endDocuments(); + return Out; +} + // Provide better error message about types missing a trait specialization template <typename T> inline typename std::enable_if<missingTraits<T, EmptyContext>::value, @@ -1476,6 +1545,18 @@ template <typename T> struct SequenceTra } }; +/// Implementation of CustomMappingTraits for std::map<std::string, T>. +template <typename T> struct StdMapStringCustomMappingTraitsImpl { + typedef std::map<std::string, T> map_type; + static void inputOne(IO &io, StringRef key, map_type &v) { + io.mapRequired(key.str().c_str(), v[key]); + } + static void output(IO &io, map_type &v) { + for (auto &p : v) + io.mapRequired(p.first.c_str(), p.second); + } +}; + } // end namespace yaml } // end namespace llvm @@ -1530,4 +1611,15 @@ template <typename T> struct SequenceTra } \ } +/// Utility for declaring that std::map<std::string, _type> should be considered +/// a YAML map. +#define LLVM_YAML_IS_STRING_MAP(_type) \ + namespace llvm { \ + namespace yaml { \ + template <> \ + struct CustomMappingTraits<std::map<std::string, _type>> \ + : public StdMapStringCustomMappingTraitsImpl<_type> {}; \ + } \ + } + #endif // LLVM_SUPPORT_YAMLTRAITS_H Modified: vendor/llvm/dist/lib/Analysis/ValueTracking.cpp ============================================================================== --- vendor/llvm/dist/lib/Analysis/ValueTracking.cpp Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/lib/Analysis/ValueTracking.cpp Wed Jan 4 22:11:11 2017 (r311315) @@ -2542,9 +2542,6 @@ bool llvm::CannotBeNegativeZero(const Va if (const ConstantFP *CFP = dyn_cast<ConstantFP>(V)) return !CFP->getValueAPF().isNegZero(); - // FIXME: Magic number! At the least, this should be given a name because it's - // used similarly in CannotBeOrderedLessThanZero(). A better fix may be to - // expose it as a parameter, so it can be used for testing / experimenting. if (Depth == MaxDepth) return false; // Limit search depth. @@ -2589,9 +2586,6 @@ bool llvm::CannotBeOrderedLessThanZero(c if (const ConstantFP *CFP = dyn_cast<ConstantFP>(V)) return !CFP->getValueAPF().isNegative() || CFP->getValueAPF().isZero(); - // FIXME: Magic number! At the least, this should be given a name because it's - // used similarly in CannotBeNegativeZero(). A better fix may be to - // expose it as a parameter, so it can be used for testing / experimenting. if (Depth == MaxDepth) return false; // Limit search depth. Modified: vendor/llvm/dist/lib/Bitcode/Reader/MetadataLoader.cpp ============================================================================== --- vendor/llvm/dist/lib/Bitcode/Reader/MetadataLoader.cpp Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/lib/Bitcode/Reader/MetadataLoader.cpp Wed Jan 4 22:11:11 2017 (r311315) @@ -749,7 +749,7 @@ Error MetadataLoader::MetadataLoaderImpl // handles the case where this is type ODRed with a definition needed // by the importing module, in which case the existing definition is // used. - if (IsImporting && !ImportFullTypeDefinitions && + if (IsImporting && !ImportFullTypeDefinitions && Identifier && (Tag == dwarf::DW_TAG_enumeration_type || Tag == dwarf::DW_TAG_class_type || Tag == dwarf::DW_TAG_structure_type || Modified: vendor/llvm/dist/lib/CodeGen/Analysis.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/Analysis.cpp Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/lib/CodeGen/Analysis.cpp Wed Jan 4 22:11:11 2017 (r311315) @@ -272,28 +272,10 @@ static const Value *getNoopInput(const V TLI.allowTruncateForTailCall(Op->getType(), I->getType())) { DataBits = std::min(DataBits, I->getType()->getPrimitiveSizeInBits()); NoopInput = Op; - } else if (isa<CallInst>(I)) { - // Look through call (skipping callee) - for (User::const_op_iterator i = I->op_begin(), e = I->op_end() - 1; - i != e; ++i) { - unsigned attrInd = i - I->op_begin() + 1; - if (cast<CallInst>(I)->paramHasAttr(attrInd, Attribute::Returned) && - isNoopBitcast((*i)->getType(), I->getType(), TLI)) { - NoopInput = *i; - break; - } - } - } else if (isa<InvokeInst>(I)) { - // Look through invoke (skipping BB, BB, Callee) - for (User::const_op_iterator i = I->op_begin(), e = I->op_end() - 3; - i != e; ++i) { - unsigned attrInd = i - I->op_begin() + 1; - if (cast<InvokeInst>(I)->paramHasAttr(attrInd, Attribute::Returned) && - isNoopBitcast((*i)->getType(), I->getType(), TLI)) { - NoopInput = *i; - break; - } - } + } else if (auto CS = ImmutableCallSite(I)) { + const Value *ReturnedOp = CS.getReturnedArgOperand(); + if (ReturnedOp && isNoopBitcast(ReturnedOp->getType(), I->getType(), TLI)) + NoopInput = ReturnedOp; } else if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(V)) { // Value may come from either the aggregate or the scalar ArrayRef<unsigned> InsertLoc = IVI->getIndices(); Modified: vendor/llvm/dist/lib/CodeGen/AsmPrinter/AsmPrinter.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Jan 4 22:11:11 2017 (r311315) @@ -37,6 +37,8 @@ #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCSection.h" +#include "llvm/MC/MCSectionELF.h" +#include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbolELF.h" #include "llvm/MC/MCValue.h" @@ -2610,6 +2612,61 @@ AsmPrinterHandler::~AsmPrinterHandler() void AsmPrinterHandler::markFunctionEnd() {} +// In the binary's "xray_instr_map" section, an array of these function entries +// describes each instrumentation point. When XRay patches your code, the index +// into this table will be given to your handler as a patch point identifier. +void AsmPrinter::XRayFunctionEntry::emit(int Bytes, MCStreamer *Out, + const MCSymbol *CurrentFnSym) const { + Out->EmitSymbolValue(Sled, Bytes); + Out->EmitSymbolValue(CurrentFnSym, Bytes); + auto Kind8 = static_cast<uint8_t>(Kind); + Out->EmitBytes(StringRef(reinterpret_cast<const char *>(&Kind8), 1)); + Out->EmitBytes( + StringRef(reinterpret_cast<const char *>(&AlwaysInstrument), 1)); + Out->EmitZeros(2 * Bytes - 2); // Pad the previous two entries +} + +void AsmPrinter::emitXRayTable() { + if (Sleds.empty()) + return; + + auto PrevSection = OutStreamer->getCurrentSectionOnly(); + auto Fn = MF->getFunction(); + MCSection *Section = nullptr; + if (MF->getSubtarget().getTargetTriple().isOSBinFormatELF()) { + if (Fn->hasComdat()) { + Section = OutContext.getELFSection("xray_instr_map", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC | ELF::SHF_GROUP, 0, + Fn->getComdat()->getName()); + } else { + Section = OutContext.getELFSection("xray_instr_map", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC); + } + } else if (MF->getSubtarget().getTargetTriple().isOSBinFormatMachO()) { + Section = OutContext.getMachOSection("__DATA", "xray_instr_map", 0, + SectionKind::getReadOnlyWithRel()); + } else { + llvm_unreachable("Unsupported target"); + } + + // Before we switch over, we force a reference to a label inside the + // xray_instr_map section. Since this function is always called just + // before the function's end, we assume that this is happening after + // the last return instruction. + + auto WordSizeBytes = TM.getPointerSize(); + MCSymbol *Tmp = OutContext.createTempSymbol("xray_synthetic_", true); + OutStreamer->EmitCodeAlignment(16); + OutStreamer->EmitSymbolValue(Tmp, WordSizeBytes, false); + OutStreamer->SwitchSection(Section); + OutStreamer->EmitLabel(Tmp); + for (const auto &Sled : Sleds) + Sled.emit(WordSizeBytes, OutStreamer.get(), CurrentFnSym); + + OutStreamer->SwitchSection(PrevSection); + Sleds.clear(); +} + void AsmPrinter::recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind) { auto Fn = MI.getParent()->getParent()->getFunction(); Modified: vendor/llvm/dist/lib/CodeGen/InlineSpiller.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/InlineSpiller.cpp Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/lib/CodeGen/InlineSpiller.cpp Wed Jan 4 22:11:11 2017 (r311315) @@ -1124,7 +1124,7 @@ void HoistSpillHelper::rmRedundantSpills // earlier spill with smaller SlotIndex. for (const auto CurrentSpill : Spills) { MachineBasicBlock *Block = CurrentSpill->getParent(); - MachineDomTreeNode *Node = MDT.DT->getNode(Block); + MachineDomTreeNode *Node = MDT.getBase().getNode(Block); MachineInstr *PrevSpill = SpillBBToSpill[Node]; if (PrevSpill) { SlotIndex PIdx = LIS.getInstructionIndex(*PrevSpill); @@ -1132,9 +1132,9 @@ void HoistSpillHelper::rmRedundantSpills MachineInstr *SpillToRm = (CIdx > PIdx) ? CurrentSpill : PrevSpill; MachineInstr *SpillToKeep = (CIdx > PIdx) ? PrevSpill : CurrentSpill; SpillsToRm.push_back(SpillToRm); - SpillBBToSpill[MDT.DT->getNode(Block)] = SpillToKeep; + SpillBBToSpill[MDT.getBase().getNode(Block)] = SpillToKeep; } else { - SpillBBToSpill[MDT.DT->getNode(Block)] = CurrentSpill; + SpillBBToSpill[MDT.getBase().getNode(Block)] = CurrentSpill; } } for (const auto SpillToRm : SpillsToRm) @@ -1209,7 +1209,7 @@ void HoistSpillHelper::getVisitOrders( // Sort the nodes in WorkSet in top-down order and save the nodes // in Orders. Orders will be used for hoisting in runHoistSpills. unsigned idx = 0; - Orders.push_back(MDT.DT->getNode(Root)); + Orders.push_back(MDT.getBase().getNode(Root)); do { MachineDomTreeNode *Node = Orders[idx++]; const std::vector<MachineDomTreeNode *> &Children = Node->getChildren(); Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jan 4 22:11:11 2017 (r311315) @@ -4277,7 +4277,8 @@ struct BaseIndexOffset { } /// Parses tree in Ptr for base, index, offset addresses. - static BaseIndexOffset match(SDValue Ptr, SelectionDAG &DAG) { + static BaseIndexOffset match(SDValue Ptr, SelectionDAG &DAG, + int64_t PartialOffset = 0) { bool IsIndexSignExt = false; // Split up a folded GlobalAddress+Offset into its component parts. @@ -4286,7 +4287,7 @@ struct BaseIndexOffset { return BaseIndexOffset(DAG.getGlobalAddress(GA->getGlobal(), SDLoc(GA), GA->getValueType(0), - /*Offset=*/0, + /*Offset=*/PartialOffset, /*isTargetGA=*/false, GA->getTargetFlags()), SDValue(), @@ -4298,14 +4299,13 @@ struct BaseIndexOffset { // instruction, then it could be just the BASE or everything else we don't // know how to handle. Just use Ptr as BASE and give up. if (Ptr->getOpcode() != ISD::ADD) - return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt); + return BaseIndexOffset(Ptr, SDValue(), PartialOffset, IsIndexSignExt); // We know that we have at least an ADD instruction. Try to pattern match // the simple case of BASE + OFFSET. if (isa<ConstantSDNode>(Ptr->getOperand(1))) { int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue(); - return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset, - IsIndexSignExt); + return match(Ptr->getOperand(0), DAG, Offset + PartialOffset); } // Inside a loop the current BASE pointer is calculated using an ADD and a @@ -4314,7 +4314,7 @@ struct BaseIndexOffset { // (i64 mul (i64 %induction_var) // (i64 %element_size))) if (Ptr->getOperand(1)->getOpcode() == ISD::MUL) - return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt); + return BaseIndexOffset(Ptr, SDValue(), PartialOffset, IsIndexSignExt); // Look at Base + Index + Offset cases. SDValue Base = Ptr->getOperand(0); @@ -4328,14 +4328,14 @@ struct BaseIndexOffset { // Either the case of Base + Index (no offset) or something else. if (IndexOffset->getOpcode() != ISD::ADD) - return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt); + return BaseIndexOffset(Base, IndexOffset, PartialOffset, IsIndexSignExt); // Now we have the case of Base + Index + offset. SDValue Index = IndexOffset->getOperand(0); SDValue Offset = IndexOffset->getOperand(1); if (!isa<ConstantSDNode>(Offset)) - return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt); + return BaseIndexOffset(Ptr, SDValue(), PartialOffset, IsIndexSignExt); // Ignore signextends. if (Index->getOpcode() == ISD::SIGN_EXTEND) { @@ -4344,7 +4344,7 @@ struct BaseIndexOffset { } else IsIndexSignExt = false; int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue(); - return BaseIndexOffset(Base, Index, Off, IsIndexSignExt); + return BaseIndexOffset(Base, Index, Off + PartialOffset, IsIndexSignExt); } }; } // namespace Modified: vendor/llvm/dist/lib/ExecutionEngine/OProfileJIT/OProfileJITEventListener.cpp ============================================================================== --- vendor/llvm/dist/lib/ExecutionEngine/OProfileJIT/OProfileJITEventListener.cpp Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/lib/ExecutionEngine/OProfileJIT/OProfileJITEventListener.cpp Wed Jan 4 22:11:11 2017 (r311315) @@ -88,15 +88,15 @@ void OProfileJITEventListener::NotifyObj // Use symbol info to iterate functions in the object. for (const std::pair<SymbolRef, uint64_t> &P : computeSymbolSizes(DebugObj)) { SymbolRef Sym = P.first; - if (Sym.getType() != SymbolRef::ST_Function) + if (!Sym.getType() || *Sym.getType() != SymbolRef::ST_Function) continue; - ErrorOr<StringRef> NameOrErr = Sym.getName(); - if (NameOrErr.getError()) + Expected<StringRef> NameOrErr = Sym.getName(); + if (!NameOrErr) continue; StringRef Name = *NameOrErr; - ErrorOr<uint64_t> AddrOrErr = Sym.getAddress(); - if (AddrOrErr.getError()) + Expected<uint64_t> AddrOrErr = Sym.getAddress(); + if (!AddrOrErr) continue; uint64_t Addr = *AddrOrErr; uint64_t Size = P.second; @@ -128,9 +128,9 @@ void OProfileJITEventListener::NotifyFre for (symbol_iterator I = DebugObj.symbol_begin(), E = DebugObj.symbol_end(); I != E; ++I) { - if (I->getType() == SymbolRef::ST_Function) { - ErrorOr<uint64_t> AddrOrErr = I->getAddress(); - if (AddrOrErr.getError()) + if (I->getType() && *I->getType() == SymbolRef::ST_Function) { + Expected<uint64_t> AddrOrErr = I->getAddress(); + if (!AddrOrErr) continue; uint64_t Addr = *AddrOrErr; Modified: vendor/llvm/dist/lib/Fuzzer/FuzzerTracePC.cpp ============================================================================== --- vendor/llvm/dist/lib/Fuzzer/FuzzerTracePC.cpp Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/lib/Fuzzer/FuzzerTracePC.cpp Wed Jan 4 22:11:11 2017 (r311315) @@ -80,6 +80,7 @@ static bool IsInterestingCoverageFile(st } void TracePC::InitializePrintNewPCs() { + if (!DoPrintNewPCs) return; assert(!PrintedPCs); PrintedPCs = new std::set<uintptr_t>; for (size_t i = 1; i < GetNumPCs(); i++) @@ -88,6 +89,7 @@ void TracePC::InitializePrintNewPCs() { } void TracePC::PrintNewPCs() { + if (!DoPrintNewPCs) return; assert(PrintedPCs); for (size_t i = 1; i < GetNumPCs(); i++) if (PCs[i] && PrintedPCs->insert(PCs[i]).second) Modified: vendor/llvm/dist/lib/IR/AutoUpgrade.cpp ============================================================================== --- vendor/llvm/dist/lib/IR/AutoUpgrade.cpp Wed Jan 4 22:06:14 2017 (r311314) +++ vendor/llvm/dist/lib/IR/AutoUpgrade.cpp Wed Jan 4 22:11:11 2017 (r311315) @@ -342,8 +342,10 @@ static bool UpgradeIntrinsicFunction1(Fu Name == "avx.cvt.ps2.pd.256" || // Added in 3.9 Name.startswith("avx.vinsertf128.") || // Added in 3.7 Name == "avx2.vinserti128" || // Added in 3.7 + Name.startswith("avx512.mask.insert") || // Added in 4.0 Name.startswith("avx.vextractf128.") || // Added in 3.7 Name == "avx2.vextracti128" || // Added in 3.7 + Name.startswith("avx512.mask.vextract") || // Added in 4.0 Name.startswith("sse4a.movnt.") || // Added in 3.9 Name.startswith("avx.movnt.") || // Added in 3.2 Name.startswith("avx512.storent.") || // Added in 3.9 @@ -1150,21 +1152,25 @@ void llvm::UpgradeIntrinsicCall(CallInst Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); } else if (IsX86 && (Name.startswith("avx.vinsertf128.") || - Name == "avx2.vinserti128")) { + Name == "avx2.vinserti128" || + Name.startswith("avx512.mask.insert"))) { Value *Op0 = CI->getArgOperand(0); Value *Op1 = CI->getArgOperand(1); unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); - VectorType *VecTy = cast<VectorType>(CI->getType()); - unsigned NumElts = VecTy->getNumElements(); + unsigned DstNumElts = CI->getType()->getVectorNumElements(); + unsigned SrcNumElts = Op1->getType()->getVectorNumElements(); + unsigned Scale = DstNumElts / SrcNumElts; // Mask off the high bits of the immediate value; hardware ignores those. - Imm = Imm & 1; + Imm = Imm % Scale; - // Extend the second operand into a vector that is twice as big. + // Extend the second operand into a vector the size of the destination. Value *UndefV = UndefValue::get(Op1->getType()); - SmallVector<uint32_t, 8> Idxs(NumElts); - for (unsigned i = 0; i != NumElts; ++i) + SmallVector<uint32_t, 8> Idxs(DstNumElts); + for (unsigned i = 0; i != SrcNumElts; ++i) Idxs[i] = i; + for (unsigned i = SrcNumElts; i != DstNumElts; ++i) + Idxs[i] = SrcNumElts; Rep = Builder.CreateShuffleVector(Op1, UndefV, Idxs); // Insert the second operand into the first operand. @@ -1178,33 +1184,41 @@ void llvm::UpgradeIntrinsicCall(CallInst // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 > - // The low half of the result is either the low half of the 1st operand - // or the low half of the 2nd operand (the inserted vector). - for (unsigned i = 0; i != NumElts / 2; ++i) - Idxs[i] = Imm ? i : (i + NumElts); - // The high half of the result is either the low half of the 2nd operand - // (the inserted vector) or the high half of the 1st operand. - for (unsigned i = NumElts / 2; i != NumElts; ++i) - Idxs[i] = Imm ? (i + NumElts / 2) : i; + // First fill with identify mask. + for (unsigned i = 0; i != DstNumElts; ++i) + Idxs[i] = i; + // Then replace the elements where we need to insert. + for (unsigned i = 0; i != SrcNumElts; ++i) + Idxs[i + Imm * SrcNumElts] = i + DstNumElts; Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs); + + // If the intrinsic has a mask operand, handle that. + if (CI->getNumArgOperands() == 5) + Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, + CI->getArgOperand(3)); } else if (IsX86 && (Name.startswith("avx.vextractf128.") || - Name == "avx2.vextracti128")) { + Name == "avx2.vextracti128" || + Name.startswith("avx512.mask.vextract"))) { Value *Op0 = CI->getArgOperand(0); unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); - VectorType *VecTy = cast<VectorType>(CI->getType()); - unsigned NumElts = VecTy->getNumElements(); + unsigned DstNumElts = CI->getType()->getVectorNumElements(); + unsigned SrcNumElts = Op0->getType()->getVectorNumElements(); + unsigned Scale = SrcNumElts / DstNumElts; // Mask off the high bits of the immediate value; hardware ignores those. - Imm = Imm & 1; + Imm = Imm % Scale; - // Get indexes for either the high half or low half of the input vector. - SmallVector<uint32_t, 4> Idxs(NumElts); - for (unsigned i = 0; i != NumElts; ++i) { - Idxs[i] = Imm ? (i + NumElts) : i; + // Get indexes for the subvector of the input vector. + SmallVector<uint32_t, 8> Idxs(DstNumElts); + for (unsigned i = 0; i != DstNumElts; ++i) { + Idxs[i] = i + (Imm * DstNumElts); } + Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); - Value *UndefV = UndefValue::get(Op0->getType()); - Rep = Builder.CreateShuffleVector(Op0, UndefV, Idxs); + // If the intrinsic has a mask operand, handle that. + if (CI->getNumArgOperands() == 4) *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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