From owner-freebsd-current@FreeBSD.ORG Sun Jun 24 03:31:09 2007 Return-Path: X-Original-To: freebsd-current@freebsd.org Delivered-To: freebsd-current@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 249ED16A41F for ; Sun, 24 Jun 2007 03:31:09 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id D825313C448 for ; Sun, 24 Jun 2007 03:31:08 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from localhost (localhost [127.0.0.1]) by harmony.bsdimp.com (8.13.8/8.13.4) with ESMTP id l5O3SvQj087259; Sat, 23 Jun 2007 21:28:58 -0600 (MDT) (envelope-from imp@bsdimp.com) Date: Sat, 23 Jun 2007 21:29:32 -0600 (MDT) Message-Id: <20070623.212932.-524876153.imp@bsdimp.com> To: alex.wilkinson@dsto.defence.gov.au From: "M. Warner Losh" In-Reply-To: <20070617071303.GG12027@obelix.dsto.defence.gov.au> References: <20070617053746.GV4602@funkthat.com> <20070616.235659.-1947354616.imp@bsdimp.com> <20070617071303.GG12027@obelix.dsto.defence.gov.au> X-Mailer: Mew version 5.2 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-2.0 (harmony.bsdimp.com [127.0.0.1]); Sat, 23 Jun 2007 21:28:58 -0600 (MDT) Cc: freebsd-current@freebsd.org Subject: Re: kernel panic with pccard insert on recent 7.0 CURRENT X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Jun 2007 03:31:09 -0000 In message: <20070617071303.GG12027@obelix.dsto.defence.gov.au> "Wilkinson, Alex" writes: : 0n Sat, Jun 16, 2007 at 11:56:59PM -0600, M. Warner Losh wrote: : : >Yes. I'm pretty sure that's wrong. All ISA and PC Card devices use : >edge triggered interrupts. Also, it is inefficient for level : >triggered interrupts, since two interrupt sources on the same : >interrupt may trigger at about the same time... : : What is meant by "edge triggered interrupts" ? An edge triggered interrupt causes the PIC to signal the CPU when there's a change in level of the interrupt line. ISA signals this way, where IRQs are normally high and the card forces them low and the bus termination pulls them back up high. This is in contrast to level triggered interrupts which are considered active the entire time they are asserted. Warner