From owner-freebsd-net@FreeBSD.ORG Sat Nov 19 00:21:45 2011 Return-Path: Delivered-To: freebsd-net@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id C8104106566B; Sat, 19 Nov 2011 00:21:45 +0000 (UTC) (envelope-from bhutchings@solarflare.com) Received: from exchange.solarflare.com (exchange.solarflare.com [216.237.3.220]) by mx1.freebsd.org (Postfix) with ESMTP id A2C628FC17; Sat, 19 Nov 2011 00:21:45 +0000 (UTC) Received: from OCEX02.SolarFlarecom.com ([10.20.40.31]) by exchange.solarflare.com with Microsoft SMTPSVC(6.0.3790.4675); Fri, 18 Nov 2011 16:21:44 -0800 Received: from [10.17.20.137] (10.17.20.137) by ocex02.SolarFlarecom.com (10.20.40.31) with Microsoft SMTP Server (TLS) id 14.1.339.1; Fri, 18 Nov 2011 16:21:44 -0800 From: Ben Hutchings To: Marius Strobl In-Reply-To: <20111118233504.GK93221@alchemy.franken.de> References: <1321652051.2883.76.camel@bwh-desktop> <20111118233504.GK93221@alchemy.franken.de> Content-Type: text/plain; charset="UTF-8" Organization: Solarflare Communications Date: Sat, 19 Nov 2011 00:21:41 +0000 Message-ID: <1321662101.2883.102.camel@bwh-desktop> MIME-Version: 1.0 X-Mailer: Evolution 2.32.2 (2.32.2-1.fc14) Content-Transfer-Encoding: 7bit X-Originating-IP: [10.17.20.137] X-TM-AS-Product-Ver: SMEX-8.0.0.1181-6.500.1024-18526.005 X-TM-AS-Result: No--24.532100-0.000000-31 X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-OriginalArrivalTime: 19 Nov 2011 00:21:44.0915 (UTC) FILETIME=[38027A30:01CCA651] Cc: freebsd-net@freebsd.org, Philip Paeps Subject: Re: sfxge: Remove interrupt self-test code X-BeenThere: freebsd-net@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Networking and TCP/IP with FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 19 Nov 2011 00:21:45 -0000 On Sat, 2011-11-19 at 00:35 +0100, Marius Strobl wrote: > On Fri, Nov 18, 2011 at 09:34:11PM +0000, Ben Hutchings wrote: > > sfxge: Remove interrupt self-test code > > > > It's not currently used; it didn't build on 32-bit and the previous > > build fix is incorrect. If we really implement self-tests we can do > > this again properly. > > Yes, I've also already noticed that this part of r227640 wasn't quite > correct. However Philip suggested to just leave it in for now until > we figure out what on earth the code actually is supposed to do and as > the atomic_cmpset_ptr(9) also works on LP64 and isn't more broken than > the atomic_cmpset_long(9) that was in there before (actually this should > have been atomic_cmpset_64(9) for an uint64_t, which isn't necessarily > available on ILP32 including i386 though). Probably this should have > been converted to be of type cpuset_t and to use the accessors from > as nowadays we also support more than 64 CPUs. I'm also > fine with just nuking the interrupt self-test altogether though. The hardware RX flow hash indirection table has 6-bit entries so it's not possible to use more than 64 RX queues without some kind of flow steering. So for the time being this driver sets a limit of 64 interrupts. Ben. -- Ben Hutchings, Staff Engineer, Solarflare Not speaking for my employer; that's the marketing department's job. They asked us to note that Solarflare product names are trademarked.