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From: Martin Blapp <mbr@FreeBSD.org>
Date: Wed, 5 Feb 2003 14:03:58 -0800 (PST)
To: all-committers@FreeBSD.org, legacy-committers@FreeBSD.org,
	cvs-all@FreeBSD.org
Subject: cvs commit: src/sys/dev/nge if_nge.c src/sys/dev/xe if_xe.c
         src/sys/pci if_rl.c if_ste.c if_vr.c if_wb.c if_xl.c
X-FreeBSD-CVS-Branch: RELENG_4
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mbr         2003/02/05 14:03:58 PST

  Modified files:        (Branch: RELENG_4)
    sys/dev/nge          if_nge.c 
    sys/dev/xe           if_xe.c 
    sys/pci              if_rl.c if_ste.c if_vr.c if_wb.c if_xl.c 
  Log:
  MFC:
  
  When reading PHY regs over the i2c bus, the turnaround ACK bit
  is read one clock edge too late. This bit is driven low by
  slave (as any other input data bits from slave) when the clock
  is LOW. The current code did read the bit after the clock was
  driven high again.
  
  Reviewed by:    phk
  
  Revision   Changes    Path
  1.13.2.13  +1 -1      src/sys/dev/nge/if_nge.c
  1.13.2.6   +2 -2      src/sys/dev/xe/if_xe.c
  1.38.2.14  +1 -1      src/sys/pci/if_rl.c
  1.14.2.9   +1 -1      src/sys/pci/if_ste.c
  1.26.2.12  +1 -1      src/sys/pci/if_vr.c
  1.26.2.5   +1 -1      src/sys/pci/if_wb.c
  1.72.2.25  +1 -1      src/sys/pci/if_xl.c

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