Date: Thu, 24 Feb 2022 10:04:26 GMT From: Hans Petter Selasky <hselasky@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: adcd93a41692 - stable/13 - mlx5en: Use a UMA cache zone for managing TLS send tags Message-ID: <202202241004.21OA4QQm003705@gitrepo.freebsd.org>
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The branch stable/13 has been updated by hselasky: URL: https://cgit.FreeBSD.org/src/commit/?id=adcd93a41692e45f0440c0e744b811d4fb197712 commit adcd93a41692e45f0440c0e744b811d4fb197712 Author: Hans Petter Selasky <hselasky@FreeBSD.org> AuthorDate: 2022-02-24 09:59:19 +0000 Commit: Hans Petter Selasky <hselasky@FreeBSD.org> CommitDate: 2022-02-24 09:59:19 +0000 mlx5en: Use a UMA cache zone for managing TLS send tags Instead of allocating directly from a normal zone. This way import and release are guaranteed to process all allocated and then deallocated items. Also, the release occurs in a sleepable context when caller of uma_zfree() or uma_zdestroy() can sleep itself. Sponsored by: NVIDIA Networking (cherry picked from commit 0f7b6e11c01d5360c9423d6938b160fe2d030ab0) --- sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c | 53 ++++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 22 deletions(-) diff --git a/sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c b/sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c index 359bd9bddc7f..2b1519e5fb0a 100644 --- a/sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c +++ b/sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls.c @@ -62,37 +62,45 @@ static const char *mlx5e_tls_stats_desc[] = { static void mlx5e_tls_work(struct work_struct *); static int -mlx5e_tls_tag_zinit(void *mem, int size, int flags) +mlx5e_tls_tag_import(void *arg, void **store, int cnt, int domain, int flags) { - struct mlx5e_tls_tag *ptag = mem; - - MPASS(size == sizeof(*ptag)); - - memset(ptag, 0, sizeof(*ptag)); - mtx_init(&ptag->mtx, "mlx5-tls-tag-mtx", NULL, MTX_DEF); - INIT_WORK(&ptag->work, mlx5e_tls_work); - - return (0); + struct mlx5e_tls_tag *ptag; + int i; + + for (i = 0; i != cnt; i++) { + ptag = malloc_domainset(sizeof(*ptag), M_MLX5E_TLS, + mlx5_dev_domainset(arg), flags | M_ZERO); + mtx_init(&ptag->mtx, "mlx5-tls-tag-mtx", NULL, MTX_DEF); + INIT_WORK(&ptag->work, mlx5e_tls_work); + store[i] = ptag; + } + return (i); } static void -mlx5e_tls_tag_zfini(void *mem, int size) +mlx5e_tls_tag_release(void *arg, void **store, int cnt) { - struct mlx5e_tls_tag *ptag = mem; + struct mlx5e_tls_tag *ptag; struct mlx5e_priv *priv; struct mlx5e_tls *ptls; + int i; - ptls = ptag->tls; - priv = container_of(ptls, struct mlx5e_priv, tls); + for (i = 0; i != cnt; i++) { + ptag = store[i]; + ptls = ptag->tls; + priv = container_of(ptls, struct mlx5e_priv, tls); - flush_work(&ptag->work); + flush_work(&ptag->work); - if (ptag->tisn != 0) { - mlx5_tls_close_tis(priv->mdev, ptag->tisn); - atomic_add_32(&ptls->num_resources, -1U); - } + if (ptag->tisn != 0) { + mlx5_tls_close_tis(priv->mdev, ptag->tisn); + atomic_add_32(&ptls->num_resources, -1U); + } + + mtx_destroy(&ptag->mtx); - mtx_destroy(&ptag->mtx); + free(ptag, M_MLX5E_TLS); + } } static void @@ -136,8 +144,9 @@ mlx5e_tls_init(struct mlx5e_priv *priv) snprintf(ptls->zname, sizeof(ptls->zname), "mlx5_%u_tls", device_get_unit(priv->mdev->pdev->dev.bsddev)); - ptls->zone = uma_zcreate(ptls->zname, sizeof(struct mlx5e_tls_tag), - NULL, NULL, mlx5e_tls_tag_zinit, mlx5e_tls_tag_zfini, UMA_ALIGN_CACHE, 0); + ptls->zone = uma_zcache_create(ptls->zname, + sizeof(struct mlx5e_tls_tag), NULL, NULL, NULL, NULL, + mlx5e_tls_tag_import, mlx5e_tls_tag_release, priv->mdev, 0); /* shared between RX and TX TLS */ ptls->max_resources = 1U << (MLX5_CAP_GEN(priv->mdev, log_max_dek) - 1);
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