Date: Thu, 7 Jul 2022 06:31:24 GMT From: Yuri Victorovich <yuri@FreeBSD.org> To: ports-committers@FreeBSD.org, dev-commits-ports-all@FreeBSD.org, dev-commits-ports-main@FreeBSD.org Subject: git: f7e48bea9f54 - main - cad/yosys: Correct WWW Message-ID: <202207070631.2676VOtL077076@gitrepo.freebsd.org>
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The branch main has been updated by yuri: URL: https://cgit.FreeBSD.org/ports/commit/?id=f7e48bea9f54bbaa2fe16d2e2f6785e7ae8c237e commit f7e48bea9f54bbaa2fe16d2e2f6785e7ae8c237e Author: Yuri Victorovich <yuri@FreeBSD.org> AuthorDate: 2022-07-07 06:31:06 +0000 Commit: Yuri Victorovich <yuri@FreeBSD.org> CommitDate: 2022-07-07 06:31:06 +0000 cad/yosys: Correct WWW --- cad/yosys/pkg-descr | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cad/yosys/pkg-descr b/cad/yosys/pkg-descr index eb8658b281f3..74658b809b82 100644 --- a/cad/yosys/pkg-descr +++ b/cad/yosys/pkg-descr @@ -2,4 +2,4 @@ Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. -WWW: http://www.clifford.at/yosys/ +WWW: https://yosyshq.net/yosys/
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