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Date:      Tue, 8 Mar 2011 06:59:59 +0000 (UTC)
From:      Adrian Chadd <adrian@FreeBSD.org>
To:        cvs-src-old@freebsd.org
Subject:   cvs commit: src/sys/conf files src/sys/dev/ath/ath_hal/ar5416 ar5416.h ar5416_attach.c ar5416_cal.c ar5416_reset.c src/sys/dev/ath/ath_hal/ar9002 ar9002phy.h ar9280.h ar9280_attach.c ar9280_olc.c ar9280_olc.h ar9285_reset.c ...
Message-ID:  <201103080700.p2870mUI022712@repoman.freebsd.org>

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adrian      2011-03-08 06:59:59 UTC

  FreeBSD src repository

  Modified files:
    sys/conf             files 
    sys/dev/ath/ath_hal/ar5416 ar5416.h ar5416_attach.c 
                               ar5416_cal.c ar5416_reset.c 
    sys/dev/ath/ath_hal/ar9002 ar9280.h ar9280_attach.c 
                               ar9285_reset.c 
    sys/modules/ath      Makefile 
  Added files:
    sys/dev/ath/ath_hal/ar9002 ar9002phy.h ar9280_olc.c 
                               ar9280_olc.h 
  Log:
  SVN rev 219393 on 2011-03-08 06:59:59Z by adrian
  
  Implement open-loop TX power control (OLC) for Merlin (AR9280) and
  generally tidy up the TX power programming code.
  
  Enforce that the TX power offset for Merlin is -5 dBm, rather than
  any other value programmable in the EEPROM. This requires some
  further code to be ported over from ath9k, so until that is done
  and tested, fail to attach NICs whose TX power offset isn't -5
  dBm.
  
  This improves both legacy and HT transmission on my merlin board.
  It allows for stable MCS TX up to MCS15.
  
  Specifics:
  
  * Refactor out a bunch of the TX power calibration code -
    setting/obtaining the power detector / gain boundaries,
    programming the PDADC
  * Take the -5 dBm TX power offset into account on Merlin -
    "0" in the per-rate TX power register means -5 dBm, not
    0 dBm
  * When doing OLC
  * Enforce min (0) and max (AR5416_MAX_RATE_POWER) when fiddling
    with the TX power, to avoid the TX power values from wrapping
    when low.
  * Implement the 1 dBm cck power offset when doing OLC
  * Implement temperature compensation for 2.4ghz mode when doing OLC
  * Implement an AR9280 specific TX power calibration routine which
    includes the OLC twiddles, leaving the earlier chipset path
    (AR5416, AR9160) alone
  
  Whilst here, use these refactored routines for the AR9285 TX power
  calibration/programming code and enforce correct overflow/underflow
  handling when fiddling with TX power values.
  
  Obtained from:  linux ath9k
  
  Revision  Changes    Path
  1.1571    +3 -0      src/sys/conf/files
  1.19      +35 -0     src/sys/dev/ath/ath_hal/ar5416/ar5416.h
  1.25      +20 -0     src/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
  1.18      +3 -0      src/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c
  1.28      +216 -84   src/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
  1.1       +50 -0     src/sys/dev/ath/ath_hal/ar9002/ar9002phy.h (new)
  1.3       +11 -0     src/sys/dev/ath/ath_hal/ar9002/ar9280.h
  1.10      +18 -0     src/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
  1.1       +318 -0    src/sys/dev/ath/ath_hal/ar9002/ar9280_olc.c (new)
  1.1       +53 -0     src/sys/dev/ath/ath_hal/ar9002/ar9280_olc.h (new)
  1.2       +12 -90    src/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c
  1.20      +1 -1      src/sys/modules/ath/Makefile



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