Date: Sun, 2 Nov 2003 01:46:14 -0800 (PST) From: Juli Mallett <jmallett@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 41106 for review Message-ID: <200311020946.hA29kEuY061355@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=41106 Change 41106 by jmallett@jmallett_dalek on 2003/11/02 01:45:19 Remove NetBSD TBIS, ... Affected files ... .. //depot/projects/mips/sys/mips/include/locore.h#11 edit .. //depot/projects/mips/sys/mips/mips/mips_subr.S#16 edit .. //depot/projects/mips/sys/mips/mips/pmap.c#19 edit .. //depot/projects/mips/sys/mips/mips/tlb.c#7 edit Differences ... ==== //depot/projects/mips/sys/mips/include/locore.h#11 (text+ko) ==== @@ -33,7 +33,6 @@ void mips64_TBIA(int); void mips64_TBIAP(int); -void mips64_TBIS(vm_paddr_t); void mips64_TLBRead(int, struct tlb *); void mips64_wbflush(void); @@ -44,7 +43,6 @@ #define MIPS_TBIA() mips64_TBIA(mips_num_tlb_entries) #define MIPS_TBIAP() mips64_TBIAP(mips_num_tlb_entries) -#define MIPS_TBIS mips64_TBIS /* * CPU identification, from PRID register. ==== //depot/projects/mips/sys/mips/mips/mips_subr.S#16 (text+ko) ==== @@ -234,61 +234,6 @@ END(MIPSX(TLBRead)) /* - * void mipsN_TBIS(vaddr_t va) - * - * Invalidate a TLB entry which has the given vaddr and ASID if found. - */ -LEAF_NOPROFILE(MIPSX(TBIS)) - mfc0 v1, MIPS_COP_0_STATUS # save status register - mtc0 zero, MIPS_COP_0_STATUS # disable interrupts - COP0_SYNC - - li v0, (PG_HVPN | PG_ASID | PG_R3) # XXX assumes Region3 - _MFC0 t0, MIPS_COP_0_TLB_HI # save current ASID - mfc0 t3, MIPS_COP_0_TLB_PG_MASK # save current pgMask - and a0, a0, v0 # make sure valid entryHi - _MTC0 a0, MIPS_COP_0_TLB_HI # look for the vaddr & ASID - COP0_SYNC - nop - nop - tlbp # probe the entry in question - COP0_SYNC - nop - nop - mfc0 v0, MIPS_COP_0_TLB_INDEX # see what we got - /*nop # -slip-*/ - /*nop # -slip-*/ - bltz v0, 1f # index < 0 then skip - li t1, MIPS_KSEG0_START # invalid address - sll v0, v0, 13 # PAGE_SHIFT + 1 - addu t1, t1, v0 - _MTC0 t1, MIPS_COP_0_TLB_HI # make entryHi invalid - COP0_SYNC - _MTC0 zero, MIPS_COP_0_TLB_LO0 # zero out entryLo0 - COP0_SYNC - _MTC0 zero, MIPS_COP_0_TLB_LO1 # zero out entryLo1 - COP0_SYNC - mtc0 zero, MIPS_COP_0_TLB_PG_MASK # zero out pageMask - COP0_SYNC - nop - nop - tlbwi - COP0_SYNC - nop - nop -1: - _MTC0 t0, MIPS_COP_0_TLB_HI # restore current ASID - COP0_SYNC - mtc0 t3, MIPS_COP_0_TLB_PG_MASK # restore pgMask - COP0_SYNC - nop - nop - j ra - mtc0 v1, MIPS_COP_0_STATUS # restore status register - COP0_SYNC # XXXX - not executed!! -END(MIPSX(TBIS)) - -/* * void mips3_TBIAP(int sizeofTLB) * * Invalidate TLB entries belong to per process user spaces while ==== //depot/projects/mips/sys/mips/mips/pmap.c#19 (text+ko) ==== @@ -451,7 +451,7 @@ { if (pmap->pm_active) { - MIPS_TBIS(va); + tlb_invalidate_page(va); /* XXX ensure coherency? */ } else { pmap_invalidate_asid(pmap); ==== //depot/projects/mips/sys/mips/mips/tlb.c#7 (text+ko) ==== @@ -152,9 +152,7 @@ tlb_invalidate_page(vm_offset_t va) { va &= ~PAGE_MASK; -#if 0 /* XXX NetBSD code is faulty. Invalidate ALL. */ - MIPS_TBIS(va); -#else +#if 1 /* XXX NetBSD code is faulty. Invalidate ALL. */ MIPS_TBIA(); #endif }
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