From owner-svn-src-head@FreeBSD.ORG Sun Nov 16 21:22:43 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 86460AEE; Sun, 16 Nov 2014 21:22:43 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 5A211BB1; Sun, 16 Nov 2014 21:22:43 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id sAGLMhWv012137; Sun, 16 Nov 2014 21:22:43 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id sAGLMhZh012136; Sun, 16 Nov 2014 21:22:43 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201411162122.sAGLMhZh012136@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Sun, 16 Nov 2014 21:22:43 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r274604 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 16 Nov 2014 21:22:43 -0000 Author: ian Date: Sun Nov 16 21:22:42 2014 New Revision: 274604 URL: https://svnweb.freebsd.org/changeset/base/274604 Log: Correct the sequence of busdma sync ops involved with PRE/POSTREAD syncs. We used to invalidate the cache for PREREAD alone, or writeback+invalidate for PREREAD with PREWRITE, then treat POSTREAD as a no-op. Prefetching on modern systems can lead to parts of a DMA buffer getting pulled into the caches while DMA is in progress (due to access of "nearby" data), so it's mandatory to invalidate during the POSTREAD sync even if a PREREAD invalidate also happened. In the PREREAD case the invalidate is done to ensure that there are no dirty cache lines that might get automatically evicted during the DMA, corrupting the buffer. In a PREREAD+PREWRITE case the writeback which is required for PREWRITE handling is suffficient to avoid corruption caused by eviction and no invalidate need be done until POSTREAD time. Submitted by: Michal Meloun Modified: head/sys/arm/arm/busdma_machdep-v6.c Modified: head/sys/arm/arm/busdma_machdep-v6.c ============================================================================== --- head/sys/arm/arm/busdma_machdep-v6.c Sun Nov 16 20:59:27 2014 (r274603) +++ head/sys/arm/arm/busdma_machdep-v6.c Sun Nov 16 21:22:42 2014 (r274604) @@ -1416,6 +1416,7 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus switch (op) { case BUS_DMASYNC_PREWRITE: + case BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD: while (sl != end) { cpu_dcache_wb_range(sl->vaddr, sl->datacount); l2cache_wb_range(sl->vaddr, sl->busaddr, @@ -1433,19 +1434,19 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus } break; - case BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD: - while (sl != end) { - cpu_dcache_wbinv_range(sl->vaddr, sl->datacount); - l2cache_wbinv_range(sl->vaddr, - sl->busaddr, sl->datacount); - sl++; - } + case BUS_DMASYNC_POSTWRITE: break; case BUS_DMASYNC_POSTREAD: - case BUS_DMASYNC_POSTWRITE: case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE: + while (sl != end) { + l2cache_inv_range(sl->vaddr, sl->busaddr, + sl->datacount); + cpu_dcache_inv_range(sl->vaddr, sl->datacount); + sl++; + } break; + default: panic("unsupported combination of sync operations: 0x%08x\n", op); break;