From owner-p4-projects@FreeBSD.ORG Fri Jan 25 16:18:15 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 1F5DA16A49E; Fri, 25 Jan 2008 16:18:15 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id BDD3916A517 for ; Fri, 25 Jan 2008 16:18:14 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id B9EB613C46B for ; Fri, 25 Jan 2008 16:18:14 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m0PGIElc050019 for ; Fri, 25 Jan 2008 16:18:14 GMT (envelope-from rrs@cisco.com) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m0PGIDZ3050016 for perforce@freebsd.org; Fri, 25 Jan 2008 16:18:13 GMT (envelope-from rrs@cisco.com) Date: Fri, 25 Jan 2008 16:18:13 GMT Message-Id: <200801251618.m0PGIDZ3050016@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to rrs@cisco.com using -f From: "Randall R. Stewart" To: Perforce Change Reviews Cc: Subject: PERFORCE change 134091 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Jan 2008 16:18:15 -0000 http://perforce.freebsd.org/chv.cgi?CH=134091 Change 134091 by rrs@rrs-mips2-jnpr on 2008/01/25 16:17:26 Gets it so the serial driver compiles. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/conf/OCTEON_rrs#1 add .. //depot/projects/mips2-jnpr/src/sys/mips/mips/tick.c#3 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/bus_octeon.h#1 add .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/cpuinfo_octeon.h#1 branch .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/files.octeon32#5 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/octeon_machdep.c#1 add .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/octeon_pcmap_regs.h#1 branch .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/std.octeon32#4 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_bus_octeonusart.c#4 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_cpu_octeonusart.c#4 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_dev_oct16550.c#3 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/tick.c#3 (text+ko) ==== @@ -72,6 +72,14 @@ 800, /* quality (adjusted in code) */ }; +void tick_early_init (uint32_t clock_hz) +{ + /* Cavium early init code */ + counter_freq = clock_hz; + counts_per_usec = (clock_hz / (1000 * 1000)); +} + + static uint64_t tick_ticker(void) { @@ -141,6 +149,8 @@ return (mips_rd_count()); } +#ifdef __DUPLCATE_OUT_WARNER +/* fix me */ /* * Wait for about n microseconds (at least!). */ @@ -172,6 +182,7 @@ } } } +#endif int sysbeep(int pitch, int period) ==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/files.octeon32#5 (text+ko) ==== @@ -5,8 +5,9 @@ mips/mips32/octeon32/uart_cpu_octeonusart.c optional uart mips/mips32/octeon32/uart_bus_octeonusart.c optional uart mips/mips32/octeon32/uart_dev_oct16550.c optional uart +mips/mips/tick.c standard #mips/mips/mp_machdep.c optional smp -#mips/mips4k/octeon32/octeon_machdep.c standard +mips/mips32/octeon32/octeon_machdep.c standard #mips/mips4k/octeon32/octeon_pci.c standard #dev/flash/octeon_ebt3000_cf.c optional cf ==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/std.octeon32#4 (text+ko) ==== ==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_bus_octeonusart.c#4 (text+ko) ==== @@ -60,6 +60,9 @@ #include "uart_if.h" +extern struct uart_class uart_oct16550_class; + + static int uart_octeon_probe(device_t dev); static void octeon_uart_identify(driver_t * drv, device_t parent); ==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_cpu_octeonusart.c#4 (text+ko) ==== @@ -53,6 +53,7 @@ bus_space_tag_t uart_bus_space_io; bus_space_tag_t uart_bus_space_mem; +extern struct uart_class uart_oct16550_class; extern struct uart_ops octeon_usart_ops; extern struct bus_space octeon_bs_tag; ==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_dev_oct16550.c#3 (text+ko) ==== @@ -71,6 +71,15 @@ #include +/* Octeon specific includes with loads of in-lines */ +#include +#include + +/* Cavium specific defines pulled from there update of ns16559.h */ +#define IIR_BUSY 0x7 +#define com_usr 39 /* Octeon 16750/16550 Uart Status Reg */ +#define REG_USR com_usr +#define USR_TXFIFO_NOTFULL 2 /* Uart TX FIFO Not full */ #include "uart_if.h"