Date: Tue, 29 Jun 2010 01:00:56 +0530 From: "Jayachandran C." <c.jayachandran@gmail.com> To: Luiz Otavio O Souza <lists.br@gmail.com> Cc: freebsd-mips@freebsd.org Subject: Re: Merging 64 bit changes to -HEAD Message-ID: <AANLkTint7Hyf79EH29OLsIfreQRd7dQMdvX9wRq4v_yG@mail.gmail.com> In-Reply-To: <3C0AEF9B-AE0C-4459-A4E1-2C8C30C10FD6@gmail.com> References: <AANLkTik8jFkB7FTIIhyjalkfv1c0yXqse57Jzz527uf_@mail.gmail.com> <897604F6-95C4-49A8-B11F-277A74C8DBAE@gmail.com> <AANLkTilfW_zOFKuIa0gJ3ahTo-vGC1VNk99a1H24uFRq@mail.gmail.com> <AANLkTil78NFxH016C7MntD8L3d4rFlCudJ0Lv22L0KCb@mail.gmail.com> <3C0AEF9B-AE0C-4459-A4E1-2C8C30C10FD6@gmail.com>
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[-- Attachment #1 --] On Mon, Jun 28, 2010 at 9:42 PM, Luiz Otavio O Souza <lists.br@gmail.com> wrote: > On Jun 28, 2010, at 7:14 AM, Jayachandran C. wrote: > >> On Sun, Jun 27, 2010 at 8:20 PM, Jayachandran C. >> <c.jayachandran@gmail.com> wrote: >>> On Sun, Jun 27, 2010 at 4:00 PM, Luiz Otavio O Souza <lists.br@gmail.com> wrote: >>>> On Jun 15, 2010, at 10:36 AM, Jayachandran C. wrote: >>>> >>>> ( ... ) >>>>> >>>>> I've tested this on XLR, but there is a chance that this might break >>>>> other platforms. So please let me know your comments on both the >>>>> patches and the merge process. >>>>> >>>>> The future patches (if everything goes well), will do the PTE_ flag to >>>>> PG_ flag renaming in Juli's tree, then the actual n32/n64 changes. >>>>> >>>>> Thanks, >>>>> JC. >>>> >>>> JC, >>>> >>>> I can't boot the ar71xx kernel after r209243: >>>> >>>> http://mips.pastebin.com/CBhe6hzR >>>> http://pastebin.com/nrRdm1UF >>>> >>>> Everything works fine with the previous revision (r209048). >>>> >>>> If you need anything else, just let me know. >>> >>> Let me have a look at this, thanks for the report. >> >> Can you enable 'TRAP_DEBUG' in sys/mips/mips/trap.c and see if you can >> get the trap information printed. Adding a line >> #define TRAP_DEBUG >> after all the #includes in trap.c should do it. This should print the >> pc, ra, and badvaddr which would help a lot in debugging. >> >> In the meantime I will look at the code again and see if I can find >> anything obviously wrong. >> >> Thanks, >> JC. > > JC, > > The TRAP_DEBUG option doesn't help, but during the tests i found a weird symptom... > > After a cold reset the kernel always hang at same place (after the WITNESS notice), but if i boot from an old kernel and issue a 'reboot' the board boots just fine. > > I've add a few printfs all around to find where it hangs and this happen at the first call of pmap_map() at vm_page_startup(). > > Here is a dmesg from a failed boot: http://mips.pastebin.com/QnUu56hD > > And here is a successful one: http://mips.pastebin.com/bsJ4Ac3z > > I hope this can give you some clue about what's is going on... Thanks for the the update. Looks like pmap_map for kernel is failing, may be the new tlb_update code causes this. Can you apply the attached patch and see if the problem still persists, it replaces the new tlb_update code with the older version. Obviously not a fix, but if we can narrow it down to this function, fixing will be easier. JC. [-- Attachment #2 --] Index: sys/conf/files.mips =================================================================== --- sys/conf/files.mips (revision 209521) +++ sys/conf/files.mips (working copy) @@ -45,6 +45,7 @@ mips/mips/pm_machdep.c standard mips/mips/swtch.S standard mips/mips/tlb.c standard +mips/mips/tlbs.S standard mips/mips/bus_space_generic.c standard mips/mips/busdma_machdep.c standard Index: sys/mips/mips/tlb.c =================================================================== --- sys/mips/mips/tlb.c (revision 209521) +++ sys/mips/mips/tlb.c (working copy) @@ -214,9 +214,18 @@ } } +void Mips_TLBUpdate(vm_offset_t, unsigned); + void tlb_update(struct pmap *pmap, vm_offset_t va, pt_entry_t pte) { + if (pmap == kernel_pmap) + va = TLBHI_ENTRY(va, 0); + else + va = TLBHI_ENTRY(va, pmap_asid(pmap)); + + Mips_TLBUpdate(va, pte); +#if 0 register_t mask, asid; register_t s; int i; @@ -246,6 +255,7 @@ mips_wr_entryhi(asid); mips_wr_pagemask(mask); intr_restore(s); +#endif } static void Index: sys/mips/mips/tlbs.S =================================================================== --- sys/mips/mips/tlbs.S (revision 0) +++ sys/mips/mips/tlbs.S (revision 0) @@ -0,0 +1,198 @@ +/* $OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $ */ +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Digital Equipment Corporation and Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Copyright (C) 1989 Digital Equipment Corporation. + * Permission to use, copy, modify, and distribute this software and + * its documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appears in all copies. + * Digital Equipment Corporation makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s, + * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL) + * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s, + * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL) + * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s, + * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL) + * + * from: @(#)locore.s 8.5 (Berkeley) 1/4/94 + * JNPR: tlb.S,v 1.1.4.2 2007/09/10 09:02:05 girish + * $FreeBSD: head/sys/mips/mips/tlb.S 206746 2010-04-17 07:20:01Z jmallett $ + */ + +/* + * Contains code that is the first executed at boot time plus + * assembly language support routines. + */ + +#include "opt_cputype.h" + +#include <machine/asm.h> +#include <machine/cpu.h> +#include <machine/cpuregs.h> +#include <machine/regnum.h> +#include <machine/pte.h> + +#include "assym.s" + +#if defined(ISA_MIPS32) +#undef WITH_64BIT_CP0 +#elif defined(ISA_MIPS64) +#define WITH_64BIT_CP0 +#elif defined(ISA_MIPS3) +#define WITH_64BIT_CP0 +#else +#error "Please write the code for this ISA" +#endif + +#ifdef WITH_64BIT_CP0 +#define _SLL dsll +#define _SRL dsrl +#define _MFC0 dmfc0 +#define _MTC0 dmtc0 +#define WIRED_SHIFT 34 +#else +#define _SLL sll +#define _SRL srl +#define _MFC0 mfc0 +#define _MTC0 mtc0 +#define WIRED_SHIFT 2 +#endif + .set noreorder # Noreorder is default style! +#if defined(ISA_MIPS32) + .set mips32 +#elif defined(ISA_MIPS64) + .set mips64 +#elif defined(ISA_MIPS3) + .set mips3 +#endif + +#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop; + +/* + * FREEBSD_DEVELOPERS_FIXME + * Some MIPS CPU may need delays using nops between executing CP0 Instructions + */ +#define MIPS_CPU_NOP_DELAY nop;nop;nop;nop; + +#undef PTE_HVPN +#undef PTE_ASID +#define PTE_HVPN 0xffffe000 /* Hardware page no mask */ +#define PTE_ASID 0x000000ff /* Address space ID */ + + + +/*-------------------------------------------------------------------------- + * + * Mips_TLBUpdate(unsigned virpageadr, lowregx); + * + * Update the TLB if highreg is found; otherwise, enter the data. + * + * Results: + * < 0 if loaded >= 0 if updated. + * + * Side effects: + * None. + * + *-------------------------------------------------------------------------- + */ +LEAF(Mips_TLBUpdate) + mfc0 v1, COP_0_STATUS_REG # Save the status register. + mtc0 zero, COP_0_STATUS_REG # Disable interrupts + ITLBNOPFIX + and t1, a0, 0x1000 # t1 = Even/Odd flag + li v0, (PTE_HVPN | PTE_ASID) + and a0, a0, v0 + _MFC0 t0, COP_0_TLB_HI # Save current PID + _MTC0 a0, COP_0_TLB_HI # Init high reg + and a2, a1, PTE_G # Copy global bit + MIPS_CPU_NOP_DELAY + tlbp # Probe for the entry. + _SLL a1, a1, WIRED_SHIFT + _SRL a1, a1, WIRED_SHIFT + nop + mfc0 v0, COP_0_TLB_INDEX # See what we got + bne t1, zero, 2f # Decide even odd +# EVEN + nop + bltz v0, 1f # index < 0 => !found + MIPS_CPU_NOP_DELAY + + tlbr # update, read entry first + MIPS_CPU_NOP_DELAY + _MTC0 a1, COP_0_TLB_LO0 # init low reg0. + MIPS_CPU_NOP_DELAY + tlbwi # update slot found + b 4f + nop +1: + mtc0 zero, COP_0_TLB_PG_MASK # init mask. + _MTC0 a0, COP_0_TLB_HI # init high reg. + _MTC0 a1, COP_0_TLB_LO0 # init low reg0. + _MTC0 a2, COP_0_TLB_LO1 # init low reg1. + MIPS_CPU_NOP_DELAY + tlbwr # enter into a random slot + MIPS_CPU_NOP_DELAY + b 4f + nop +# ODD +2: + nop + bltz v0, 3f # index < 0 => !found + MIPS_CPU_NOP_DELAY + + tlbr # read the entry first + MIPS_CPU_NOP_DELAY + _MTC0 a1, COP_0_TLB_LO1 # init low reg1. + MIPS_CPU_NOP_DELAY + tlbwi # update slot found + MIPS_CPU_NOP_DELAY + b 4f + nop +3: + mtc0 zero, COP_0_TLB_PG_MASK # init mask. + _MTC0 a0, COP_0_TLB_HI # init high reg. + _MTC0 a2, COP_0_TLB_LO0 # init low reg0. + _MTC0 a1, COP_0_TLB_LO1 # init low reg1. + MIPS_CPU_NOP_DELAY + tlbwr # enter into a random slot + +4: # Make shure pipeline + MIPS_CPU_NOP_DELAY + _MTC0 t0, COP_0_TLB_HI # restore PID + mtc0 v1, COP_0_STATUS_REG # Restore the status register + ITLBNOPFIX + j ra + nop +END(Mips_TLBUpdate) +
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