Date: Mon, 6 May 2013 14:54:17 +0000 (UTC) From: Grzegorz Bernacki <gber@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r250295 - head/sys/arm/mv Message-ID: <201305061454.r46EsHNt032762@svn.freebsd.org>
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Author: gber Date: Mon May 6 14:54:17 2013 New Revision: 250295 URL: http://svnweb.freebsd.org/changeset/base/250295 Log: Disable decoding windows with no FDT entry. - On ARMADAXP B0 (GP development board) we are not able to use PCI due to whole 32-bit address space used by 4GB of RAM memory. - Change is required to destroy unnecessary window to free address space for PCI and other devices - Fix offset value for SDRAM decoding windows Obtained from: Semihalf Modified: head/sys/arm/mv/common.c head/sys/arm/mv/mvvar.h head/sys/arm/mv/mvwin.h Modified: head/sys/arm/mv/common.c ============================================================================== --- head/sys/arm/mv/common.c Mon May 6 14:27:46 2013 (r250294) +++ head/sys/arm/mv/common.c Mon May 6 14:54:17 2013 (r250295) @@ -89,6 +89,7 @@ static int decode_win_xor_valid(void); #ifndef SOC_MV_FREY static void decode_win_cpu_setup(void); +static int decode_win_sdram_fixup(void); #endif static void decode_win_usb_setup(u_long); static void decode_win_eth_setup(u_long); @@ -522,6 +523,11 @@ soc_decode_win(void) /* Retrieve our ID: some windows facilities vary between SoC models */ soc_id(&dev, &rev); +#ifdef SOC_MV_ARMADAXP + if ((err = decode_win_sdram_fixup()) != 0) + return(err); +#endif + #ifndef SOC_MV_FREY if (!decode_win_cpu_valid() || !decode_win_usb_valid() || !decode_win_eth_valid() || !decode_win_idma_valid() || @@ -617,6 +623,8 @@ WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN #ifndef SOC_MV_DOVE WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) +WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) +WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) #else /* * On 88F6781 (Dove) SoC DDR Controller is accessed through @@ -871,6 +879,48 @@ decode_win_cpu_setup(void) cpu_wins[i].size, cpu_wins[i].remap); } + +static int +decode_win_sdram_fixup(void) +{ + struct mem_region mr[FDT_MEM_REGIONS]; + uint8_t window_valid[MV_WIN_DDR_MAX]; + int mr_cnt, memsize, err, i, j; + uint32_t valid_win_num = 0; + + /* Grab physical memory regions information from device tree. */ + err = fdt_get_mem_regions(mr, &mr_cnt, &memsize); + if (err != 0) + return (err); + + for (i = 0; i < MV_WIN_DDR_MAX; i++) + window_valid[i] = 0; + + /* Try to match entries from device tree with settings from u-boot */ + for (i = 0; i < mr_cnt; i++) { + for (j = 0; j < MV_WIN_DDR_MAX; j++) { + if (ddr_is_active(j) && + (ddr_base(j) == mr[i].mr_start) && + (ddr_size(j) == mr[i].mr_size)) { + window_valid[j] = 1; + valid_win_num++; + } + } + } + + if (mr_cnt != valid_win_num) + return (EINVAL); + + /* Destroy windows without corresponding device tree entry */ + for (j = 0; j < MV_WIN_DDR_MAX; j++) { + if (ddr_is_active(j) && (window_valid[j] != 1)) { + printf("Disabling SDRAM decoding window: %d\n", j); + ddr_disable(j); + } + } + + return (0); +} #endif /* * Check if we're able to cover all active DDR banks. @@ -907,6 +957,14 @@ ddr_is_active(int i) return (0); } +void +ddr_disable(int i) +{ + + ddr_sz_write(i, 0); + ddr_br_write(i, 0); +} + uint32_t ddr_base(int i) { Modified: head/sys/arm/mv/mvvar.h ============================================================================== --- head/sys/arm/mv/mvvar.h Mon May 6 14:27:46 2013 (r250294) +++ head/sys/arm/mv/mvvar.h Mon May 6 14:54:17 2013 (r250295) @@ -97,6 +97,7 @@ int decode_win_overlap(int, int, const s int win_cpu_can_remap(int); void decode_win_pcie_setup(u_long); +void ddr_disable(int i); int ddr_is_active(int i); uint32_t ddr_base(int i); uint32_t ddr_size(int i); Modified: head/sys/arm/mv/mvwin.h ============================================================================== --- head/sys/arm/mv/mvwin.h Mon May 6 14:27:46 2013 (r250294) +++ head/sys/arm/mv/mvwin.h Mon May 6 14:54:17 2013 (r250295) @@ -122,6 +122,8 @@ #define MV_DDR_CADR_BASE (MV_AXI_BASE + 0x100) #elif defined(SOC_MV_LOKIPLUS) #define MV_DDR_CADR_BASE (MV_BASE + 0xF1500) +#elif defined(SOC_MV_ARMADAXP) +#define MV_DDR_CADR_BASE (MV_BASE + 0x20180) #else #define MV_DDR_CADR_BASE (MV_BASE + 0x1500) #endif
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