From owner-freebsd-questions Thu Apr 19 13:51:12 2001 Delivered-To: freebsd-questions@freebsd.org Received: from q.closedsrc.org (ip233.gte15.rb1.bel.nwlink.com [209.20.244.233]) by hub.freebsd.org (Postfix) with ESMTP id 4BBE637B43C for ; Thu, 19 Apr 2001 13:51:09 -0700 (PDT) (envelope-from lplist@closedsrc.org) Received: by q.closedsrc.org (Postfix, from userid 1003) id 1639655407; Thu, 19 Apr 2001 13:45:36 -0700 (PDT) Received: from localhost (localhost [127.0.0.1]) by q.closedsrc.org (Postfix) with ESMTP id 0669D51610; Thu, 19 Apr 2001 13:45:36 -0700 (PDT) Date: Thu, 19 Apr 2001 13:45:36 -0700 (PDT) From: Linh Pham To: Vincent Poy Cc: Jeremiah Gowdy , Charles Burns , , , , Subject: Re: the AMD factor in FreeBSD In-Reply-To: Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: owner-freebsd-questions@FreeBSD.ORG Precedence: bulk X-Loop: FreeBSD.ORG On 2001-04-19, Vincent Poy scribbled: # Somehow I thought the Intel and AMD x86 CPUs were CISC and had a # portion that was RISC. AMD uses their RISC86 engine to turn crummy x86 instructions into RISC-like instructions to crunch them more efficiently as it can. The Pentium III processors do something like that since the P6 core, but the original P6 core sucked at 16-bit code... so Intel had to reduce the optimizations in the Out-of-Order engine to increase 16-bit performance in the Pentium II. In reality... the x86 processors and, what people tend to call, RISC processors now are really post-RISC. Trying to expand IPC and increase Mhz :) Intel went the opposite with the P4. -- Linh Pham [lplist@closedsrc.org] // 404b - Brain not found To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-questions" in the body of the message