From owner-svn-src-head@FreeBSD.ORG Fri Jun 14 21:14:37 2013 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) by hub.freebsd.org (Postfix) with ESMTP id 48A9D93; Fri, 14 Jun 2013 21:14:37 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id 2AA7B1957; Fri, 14 Jun 2013 21:14:37 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id r5ELEbLR078405; Fri, 14 Jun 2013 21:14:37 GMT (envelope-from dim@svn.freebsd.org) Received: (from dim@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id r5ELEaPx078403; Fri, 14 Jun 2013 21:14:36 GMT (envelope-from dim@svn.freebsd.org) Message-Id: <201306142114.r5ELEaPx078403@svn.freebsd.org> From: Dimitry Andric Date: Fri, 14 Jun 2013 21:14:36 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r251761 - in head/contrib/llvm/lib/Target/X86: . AsmParser X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 Jun 2013 21:14:37 -0000 Author: dim Date: Fri Jun 14 21:14:36 2013 New Revision: 251761 URL: http://svnweb.freebsd.org/changeset/base/251761 Log: Pull in r181620 from llvm trunk: [ms-inline asm] Fix a crasher when we fail on a direct match. The issue was that the MatchingInlineAsm and VariantID args to the MatchInstructionImpl function weren't being set properly. Specifically, when parsing intel syntax, the parser thought it was parsing inline assembly in the at&t dialect; that will never be the case. The crash was caused when the emitter tried to emit the instruction, but the operands weren't set. When parsing inline assembly we only set the opcode, not the operands, which is used to lookup the instruction descriptor. rdar://13854391 and PR15945 Also, this commit reverts r176036. Now that we're correctly parsing the intel syntax the pushad/popad don't match properly. I've reimplemented that fix using a MnemonicAlias. Pull in r183907 from llvm trunk: X86: Make the cmov aliases work with intel syntax too. These commits make a number of Intel-style inline assembly mnemonics aliases (occurring in several ports) work properly, which could cause assertions otherwise. Reported by: kwm, bapt Modified: head/contrib/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp head/contrib/llvm/lib/Target/X86/X86InstrInfo.td Modified: head/contrib/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp ============================================================================== --- head/contrib/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp Fri Jun 14 20:44:23 2013 (r251760) +++ head/contrib/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp Fri Jun 14 21:14:36 2013 (r251761) @@ -2306,25 +2306,25 @@ MatchAndEmitInstruction(SMLoc IDLoc, uns unsigned Match1, Match2, Match3, Match4; Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore, - isParsingIntelSyntax()); + MatchingInlineAsm, isParsingIntelSyntax()); // If this returned as a missing feature failure, remember that. if (Match1 == Match_MissingFeature) ErrorInfoMissingFeature = ErrorInfoIgnore; Tmp[Base.size()] = Suffixes[1]; Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore, - isParsingIntelSyntax()); + MatchingInlineAsm, isParsingIntelSyntax()); // If this returned as a missing feature failure, remember that. if (Match2 == Match_MissingFeature) ErrorInfoMissingFeature = ErrorInfoIgnore; Tmp[Base.size()] = Suffixes[2]; Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore, - isParsingIntelSyntax()); + MatchingInlineAsm, isParsingIntelSyntax()); // If this returned as a missing feature failure, remember that. if (Match3 == Match_MissingFeature) ErrorInfoMissingFeature = ErrorInfoIgnore; Tmp[Base.size()] = Suffixes[3]; Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore, - isParsingIntelSyntax()); + MatchingInlineAsm, isParsingIntelSyntax()); // If this returned as a missing feature failure, remember that. if (Match4 == Match_MissingFeature) ErrorInfoMissingFeature = ErrorInfoIgnore; Modified: head/contrib/llvm/lib/Target/X86/X86InstrInfo.td ============================================================================== --- head/contrib/llvm/lib/Target/X86/X86InstrInfo.td Fri Jun 14 20:44:23 2013 (r251760) +++ head/contrib/llvm/lib/Target/X86/X86InstrInfo.td Fri Jun 14 21:14:36 2013 (r251761) @@ -884,12 +884,12 @@ def PUSHF64 : I<0x9C, RawFrm, (outs), let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in { -def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l|d}", [], IIC_POP_A>, +def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", [], IIC_POP_A>, Requires<[In32BitMode]>; } let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in { -def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l|d}", [], IIC_PUSH_A>, +def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", [], IIC_PUSH_A>, Requires<[In32BitMode]>; } @@ -1867,6 +1867,9 @@ def : MnemonicAlias<"pushf", "pushfl", def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; def : MnemonicAlias<"pushfd", "pushfl", "att">; +def : MnemonicAlias<"popad", "popa", "intel">, Requires<[In32BitMode]>; +def : MnemonicAlias<"pushad", "pusha", "intel">, Requires<[In32BitMode]>; + def : MnemonicAlias<"repe", "rep", "att">; def : MnemonicAlias<"repz", "rep", "att">; def : MnemonicAlias<"repnz", "repne", "att">; @@ -1919,29 +1922,31 @@ def : MnemonicAlias<"fucomip", "fucompi def : MnemonicAlias<"fwait", "wait", "att">; -class CondCodeAlias +class CondCodeAlias : MnemonicAlias; + !strconcat(Prefix, NewCond, Suffix), VariantName>; /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for /// example "setz" -> "sete". -multiclass IntegerCondCodeMnemonicAlias { - def C : CondCodeAlias; // setc -> setb - def Z : CondCodeAlias; // setz -> sete - def NA : CondCodeAlias; // setna -> setbe - def NB : CondCodeAlias; // setnb -> setae - def NC : CondCodeAlias; // setnc -> setae - def NG : CondCodeAlias; // setng -> setle - def NL : CondCodeAlias; // setnl -> setge - def NZ : CondCodeAlias; // setnz -> setne - def PE : CondCodeAlias; // setpe -> setp - def PO : CondCodeAlias; // setpo -> setnp - - def NAE : CondCodeAlias; // setnae -> setb - def NBE : CondCodeAlias; // setnbe -> seta - def NGE : CondCodeAlias; // setnge -> setl - def NLE : CondCodeAlias; // setnle -> setg +multiclass IntegerCondCodeMnemonicAlias { + def C : CondCodeAlias; // setc -> setb + def Z : CondCodeAlias; // setz -> sete + def NA : CondCodeAlias; // setna -> setbe + def NB : CondCodeAlias; // setnb -> setae + def NC : CondCodeAlias; // setnc -> setae + def NG : CondCodeAlias; // setng -> setle + def NL : CondCodeAlias; // setnl -> setge + def NZ : CondCodeAlias; // setnz -> setne + def PE : CondCodeAlias; // setpe -> setp + def PO : CondCodeAlias; // setpo -> setnp + + def NAE : CondCodeAlias; // setnae -> setb + def NBE : CondCodeAlias; // setnbe -> seta + def NGE : CondCodeAlias; // setnge -> setl + def NLE : CondCodeAlias; // setnle -> setg } // Aliases for set @@ -1949,9 +1954,11 @@ defm : IntegerCondCodeMnemonicAlias<"set // Aliases for j defm : IntegerCondCodeMnemonicAlias<"j", "">; // Aliases for cmov{w,l,q} -defm : IntegerCondCodeMnemonicAlias<"cmov", "w">; -defm : IntegerCondCodeMnemonicAlias<"cmov", "l">; -defm : IntegerCondCodeMnemonicAlias<"cmov", "q">; +defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; +defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; +defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; +// No size suffix for intel-style asm. +defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; //===----------------------------------------------------------------------===//