From owner-svn-src-stable-10@FreeBSD.ORG Tue Feb 4 03:36:52 2014 Return-Path: Delivered-To: svn-src-stable-10@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 66767B0D; Tue, 4 Feb 2014 03:36:52 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 4E00C1B67; Tue, 4 Feb 2014 03:36:52 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s143aqa2039831; Tue, 4 Feb 2014 03:36:52 GMT (envelope-from eadler@svn.freebsd.org) Received: (from eadler@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s143ah3l039786; Tue, 4 Feb 2014 03:36:43 GMT (envelope-from eadler@svn.freebsd.org) Message-Id: <201402040336.s143ah3l039786@svn.freebsd.org> From: Eitan Adler Date: Tue, 4 Feb 2014 03:36:43 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r261455 - in stable/10: lib/libc/sparc64/fpu lib/libc/xdr sys/amd64/pci sys/amd64/vmm/intel sys/arm/arm sys/arm/at91 sys/arm/broadcom/bcm2835 sys/arm/econa sys/arm/freescale/imx sys/arm... X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable-10@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: SVN commit messages for only the 10-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Feb 2014 03:36:52 -0000 Author: eadler Date: Tue Feb 4 03:36:42 2014 New Revision: 261455 URL: http://svnweb.freebsd.org/changeset/base/261455 Log: MFC r258779,r258780,r258787,r258822: Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this shifts into the sign bit. Instead use (1U << 31) which gets the expected result. Similar to the (1 << 31) case it is not defined to do (2 << 30). This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases. A similar change was made in OpenBSD. Modified: stable/10/lib/libc/sparc64/fpu/fpu.c stable/10/lib/libc/sparc64/fpu/fpu_sqrt.c stable/10/lib/libc/xdr/xdr_rec.c stable/10/sys/amd64/pci/pci_cfgreg.c stable/10/sys/amd64/vmm/intel/vmcs.h stable/10/sys/amd64/vmm/intel/vmx_controls.h stable/10/sys/amd64/vmm/intel/vtd.c stable/10/sys/arm/arm/cpufunc_asm_pj4b.S stable/10/sys/arm/arm/db_trace.c stable/10/sys/arm/arm/pl190.c stable/10/sys/arm/at91/if_macbvar.h stable/10/sys/arm/broadcom/bcm2835/bcm2835_dma.c stable/10/sys/arm/econa/if_ece.c stable/10/sys/arm/freescale/imx/imx6_anatopreg.h stable/10/sys/arm/freescale/imx/imx6_usbphy.c stable/10/sys/arm/freescale/imx/imx_gptreg.h stable/10/sys/arm/include/armreg.h stable/10/sys/arm/lpc/if_lpereg.h stable/10/sys/arm/lpc/lpcreg.h stable/10/sys/arm/mv/mv_pci.c stable/10/sys/arm/samsung/exynos/ehci_exynos5.c stable/10/sys/arm/xscale/i8134x/i81342reg.h stable/10/sys/arm/xscale/ixp425/ixp425reg.h stable/10/sys/boot/arm/at91/libat91/mci_device.h stable/10/sys/boot/i386/libfirewire/fwohci.h stable/10/sys/boot/i386/libfirewire/fwohcireg.h stable/10/sys/dev/aac/aacvar.h stable/10/sys/dev/acpica/acpi_video.c stable/10/sys/dev/agp/agp_i810.c stable/10/sys/dev/ahci/ahci.h stable/10/sys/dev/bktr/bktr_core.c stable/10/sys/dev/cesa/cesa.h stable/10/sys/dev/drm/i915_reg.h stable/10/sys/dev/drm/mach64_drv.h stable/10/sys/dev/drm/mga_drv.h stable/10/sys/dev/drm/r128_drv.h stable/10/sys/dev/drm/r300_reg.h stable/10/sys/dev/drm/r600_blit.c stable/10/sys/dev/drm/radeon_cp.c stable/10/sys/dev/drm/radeon_drv.h stable/10/sys/dev/drm/via_irq.c stable/10/sys/dev/drm2/i915/i915_reg.h stable/10/sys/dev/drm2/radeon/evergreen_blit_kms.c stable/10/sys/dev/drm2/radeon/evergreen_cs.c stable/10/sys/dev/drm2/radeon/evergreend.h stable/10/sys/dev/drm2/radeon/nid.h stable/10/sys/dev/drm2/radeon/r200.c stable/10/sys/dev/drm2/radeon/r300.c stable/10/sys/dev/drm2/radeon/r300_reg.h stable/10/sys/dev/drm2/radeon/r500_reg.h stable/10/sys/dev/drm2/radeon/r600_blit.c stable/10/sys/dev/drm2/radeon/r600_blit_kms.c stable/10/sys/dev/drm2/radeon/r600_cs.c stable/10/sys/dev/drm2/radeon/r600d.h stable/10/sys/dev/drm2/radeon/radeon_cp.c stable/10/sys/dev/drm2/radeon/radeon_drv.h stable/10/sys/dev/drm2/radeon/radeon_reg.h stable/10/sys/dev/drm2/radeon/rv770d.h stable/10/sys/dev/drm2/radeon/sid.h stable/10/sys/dev/drm2/ttm/ttm_bo.c stable/10/sys/dev/e1000/e1000_82575.h stable/10/sys/dev/e1000/e1000_ich8lan.c stable/10/sys/dev/e1000/e1000_regs.h stable/10/sys/dev/etherswitch/arswitch/arswitchreg.h stable/10/sys/dev/ffec/if_ffecreg.h stable/10/sys/dev/firewire/firewire.c stable/10/sys/dev/firewire/fwohci.c stable/10/sys/dev/firewire/fwohcireg.h stable/10/sys/dev/firewire/sbp.c stable/10/sys/dev/firewire/sbp.h stable/10/sys/dev/firewire/sbp_targ.c stable/10/sys/dev/hatm/if_hatmreg.h stable/10/sys/dev/hwpmc/hwpmc_piv.h stable/10/sys/dev/iwn/if_iwnreg.h stable/10/sys/dev/mge/if_mgevar.h stable/10/sys/dev/mpt/mpt_cam.c stable/10/sys/dev/msk/if_mskreg.h stable/10/sys/dev/mvs/mvs.h stable/10/sys/dev/mxge/mxge_mcp.h stable/10/sys/dev/qlxge/qls_dump.c stable/10/sys/dev/ral/rt2560reg.h stable/10/sys/dev/ral/rt2661reg.h stable/10/sys/dev/ral/rt2860reg.h stable/10/sys/dev/sound/pci/hda/hdaa.h stable/10/sys/dev/usb/controller/ehci.h stable/10/sys/dev/usb/wlan/if_rumreg.h stable/10/sys/dev/usb/wlan/if_runreg.h stable/10/sys/dev/usb/wlan/if_uralreg.h stable/10/sys/dev/usb/wlan/if_urtwreg.h stable/10/sys/dev/usb/wlan/if_zydreg.h stable/10/sys/dev/wpi/if_wpireg.h stable/10/sys/geom/raid/tr_raid1e.c stable/10/sys/i386/pci/pci_cfgreg.c stable/10/sys/mips/atheros/ar71xxreg.h stable/10/sys/mips/atheros/ar934xreg.h stable/10/sys/mips/atheros/if_argevar.h stable/10/sys/mips/malta/gt_pci.c stable/10/sys/mips/nlm/dev/net/nae.c stable/10/sys/mips/nlm/xlp_machdep.c stable/10/sys/mips/rmi/pic.h stable/10/sys/ofed/drivers/infiniband/hw/mlx4/qp.c stable/10/sys/ofed/drivers/infiniband/hw/mthca/mthca_mcg.c stable/10/sys/ofed/drivers/infiniband/hw/mthca/mthca_qp.c stable/10/sys/ofed/drivers/net/mlx4/mcg.c stable/10/sys/powerpc/fpu/fpu_emu.c stable/10/sys/powerpc/fpu/fpu_sqrt.c stable/10/sys/powerpc/powermac/nvbl.c stable/10/sys/sys/consio.h stable/10/sys/x86/iommu/intel_reg.h stable/10/usr.sbin/bluetooth/bthidd/kbd.c Directory Properties: stable/10/ (props changed) Modified: stable/10/lib/libc/sparc64/fpu/fpu.c ============================================================================== --- stable/10/lib/libc/sparc64/fpu/fpu.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/lib/libc/sparc64/fpu/fpu.c Tue Feb 4 03:36:42 2014 (r261455) @@ -202,7 +202,7 @@ static const int opmask[] = {0, 0, 1, 3, * Implement a move operation for all supported operand types. The additional * nand and xor parameters will be applied to the upper 32 bit word of the * source operand. This allows to implement fabs and fneg (for fp operands - * only!) using this functions, too, by passing (1 << 31) for one of the + * only!) using this functions, too, by passing (1U << 31) for one of the * parameters, and 0 for the other. */ static void @@ -358,10 +358,10 @@ __fpu_execute(struct utrapframe *uf, str __fpu_mov(fe, type, rd, rs2, 0, 0); return (0); case FOP(INS2_FPop1, INSFP1_FNEG): - __fpu_mov(fe, type, rd, rs2, 0, (1 << 31)); + __fpu_mov(fe, type, rd, rs2, 0, (1U << 31)); return (0); case FOP(INS2_FPop1, INSFP1_FABS): - __fpu_mov(fe, type, rd, rs2, (1 << 31), 0); + __fpu_mov(fe, type, rd, rs2, (1U << 31), 0); return (0); case FOP(INS2_FPop1, INSFP1_FSQRT): __fpu_explode(fe, &fe->fe_f1, type, rs2); Modified: stable/10/lib/libc/sparc64/fpu/fpu_sqrt.c ============================================================================== --- stable/10/lib/libc/sparc64/fpu/fpu_sqrt.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/lib/libc/sparc64/fpu/fpu_sqrt.c Tue Feb 4 03:36:42 2014 (r261455) @@ -257,7 +257,7 @@ __fpu_sqrt(fe) * double x correctly while doing the `known q=1.0'. * * We do this one mantissa-word at a time, as noted above, to - * save work. To avoid `(1 << 31) << 1', we also do the top bit + * save work. To avoid `(1U << 31) << 1', we also do the top bit * outside of each per-word loop. * * The calculation `t = y + bit' breaks down into `t0 = y0, ..., Modified: stable/10/lib/libc/xdr/xdr_rec.c ============================================================================== --- stable/10/lib/libc/xdr/xdr_rec.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/lib/libc/xdr/xdr_rec.c Tue Feb 4 03:36:42 2014 (r261455) @@ -106,7 +106,7 @@ static const struct xdr_ops xdrrec_ops * meet the needs of xdr and rpc based on tcp. */ -#define LAST_FRAG ((u_int32_t)(1 << 31)) +#define LAST_FRAG ((u_int32_t)(1U << 31)) typedef struct rec_strm { char *tcp_handle; Modified: stable/10/sys/amd64/pci/pci_cfgreg.c ============================================================================== --- stable/10/sys/amd64/pci/pci_cfgreg.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/amd64/pci/pci_cfgreg.c Tue Feb 4 03:36:42 2014 (r261455) @@ -184,7 +184,7 @@ pci_cfgenable(unsigned bus, unsigned slo if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX && (unsigned)reg <= PCI_REGMAX && bytes != 3 && (unsigned)bytes <= 4 && (reg & (bytes - 1)) == 0) { - outl(CONF1_ADDR_PORT, (1 << 31) | (bus << 16) | (slot << 11) + outl(CONF1_ADDR_PORT, (1U << 31) | (bus << 16) | (slot << 11) | (func << 8) | (reg & ~0x03)); dataport = CONF1_DATA_PORT + (reg & 0x03); } Modified: stable/10/sys/amd64/vmm/intel/vmcs.h ============================================================================== --- stable/10/sys/amd64/vmm/intel/vmcs.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/amd64/vmm/intel/vmcs.h Tue Feb 4 03:36:42 2014 (r261455) @@ -318,7 +318,7 @@ uint64_t vmcs_read(uint32_t encoding); /* * VMCS IDT-Vectoring information fields */ -#define VMCS_IDT_VEC_VALID (1 << 31) +#define VMCS_IDT_VEC_VALID (1U << 31) #define VMCS_IDT_VEC_ERRCODE_VALID (1 << 11) /* Modified: stable/10/sys/amd64/vmm/intel/vmx_controls.h ============================================================================== --- stable/10/sys/amd64/vmm/intel/vmx_controls.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/amd64/vmm/intel/vmx_controls.h Tue Feb 4 03:36:42 2014 (r261455) @@ -56,7 +56,7 @@ #define PROCBASED_MSR_BITMAPS (1 << 28) #define PROCBASED_MONITOR_EXITING (1 << 29) #define PROCBASED_PAUSE_EXITING (1 << 30) -#define PROCBASED_SECONDARY_CONTROLS (1 << 31) +#define PROCBASED_SECONDARY_CONTROLS (1U << 31) /* Secondary Processor-Based VM-Execution Controls */ #define PROCBASED2_VIRTUALIZE_APIC (1 << 0) Modified: stable/10/sys/amd64/vmm/intel/vtd.c ============================================================================== --- stable/10/sys/amd64/vmm/intel/vtd.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/amd64/vmm/intel/vtd.c Tue Feb 4 03:36:42 2014 (r261455) @@ -74,11 +74,11 @@ struct vtdmap { #define VTD_GCR_WBF (1 << 27) #define VTD_GCR_SRTP (1 << 30) -#define VTD_GCR_TE (1 << 31) +#define VTD_GCR_TE (1U << 31) #define VTD_GSR_WBFS (1 << 27) #define VTD_GSR_RTPS (1 << 30) -#define VTD_GSR_TES (1 << 31) +#define VTD_GSR_TES (1U << 31) #define VTD_CCR_ICC (1UL << 63) /* invalidate context cache */ #define VTD_CCR_CIRG_GLOBAL (1UL << 61) /* global invalidation */ Modified: stable/10/sys/arm/arm/cpufunc_asm_pj4b.S ============================================================================== --- stable/10/sys/arm/arm/cpufunc_asm_pj4b.S Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/arm/cpufunc_asm_pj4b.S Tue Feb 4 03:36:42 2014 (r261455) @@ -237,7 +237,7 @@ ENTRY(pj4b_config) orr r0, r0, #(1 << 27) /* Critical word first sequencing disable */ orr r0, r0, #(1 << 29) /* Disable MO device read / write */ orr r0, r0, #(1 << 30) /* L1 cache strict round-robin replacement policy*/ - orr r0, r0, #(1 << 31) /* Enable write evict */ + orr r0, r0, #(1U << 31) /* Enable write evict */ mcr p15, 1, r0, c15, c1, 2 #if defined(SMP) /* Set SMP mode in Auxiliary Control Register */ Modified: stable/10/sys/arm/arm/db_trace.c ============================================================================== --- stable/10/sys/arm/arm/db_trace.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/arm/db_trace.c Tue Feb 4 03:36:42 2014 (r261455) @@ -376,7 +376,7 @@ db_stack_trace_cmd(struct unwind_state * index = db_find_index(state->start_pc); if (index->insn != EXIDX_CANTUNWIND) { - if (index->insn & (1 << 31)) { + if (index->insn & (1U << 31)) { /* The data is within the instruction */ state->insn = &index->insn; } else { Modified: stable/10/sys/arm/arm/pl190.c ============================================================================== --- stable/10/sys/arm/arm/pl190.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/arm/pl190.c Tue Feb 4 03:36:42 2014 (r261455) @@ -113,7 +113,7 @@ pl190_intc_attach(device_t dev) /* Disable all interrupts */ intc_vic_write_4(VICINTENCLEAR, 0xffffffff); /* Enable INT31, SIC IRQ */ - intc_vic_write_4(VICINTENABLE, (1 << 31)); + intc_vic_write_4(VICINTENABLE, (1U << 31)); id = 0; for (i = 3; i >= 0; i--) { Modified: stable/10/sys/arm/at91/if_macbvar.h ============================================================================== --- stable/10/sys/arm/at91/if_macbvar.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/at91/if_macbvar.h Tue Feb 4 03:36:42 2014 (r261455) @@ -18,7 +18,7 @@ struct eth_tx_desc { uint32_t addr; uint32_t flags; -#define TD_OWN (1 << 31) +#define TD_OWN (1U << 31) #define TD_LAST (1 << 15) #define TD_WRAP_MASK (1 << 30) }; @@ -30,7 +30,7 @@ struct eth_rx_desc { #define RD_OWN 0x00000001 uint32_t flags; -#define RD_BROADCAST (1 << 31) +#define RD_BROADCAST (1U << 31) #define RD_MULTICAST (1 << 30) #define RD_UNICAST (1 << 29) #define RD_EXTERNAL (1 << 28) Modified: stable/10/sys/arm/broadcom/bcm2835/bcm2835_dma.c ============================================================================== --- stable/10/sys/arm/broadcom/bcm2835/bcm2835_dma.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/broadcom/bcm2835/bcm2835_dma.c Tue Feb 4 03:36:42 2014 (r261455) @@ -74,7 +74,7 @@ __FBSDID("$FreeBSD$"); #define CS_WAITWRT (1 << 28) #define CS_DISDBG (1 << 29) #define CS_ABORT (1 << 30) -#define CS_RESET (1 << 31) +#define CS_RESET (1U << 31) #define BCM_DMA_CBADDR(n) (0x100*(n) + 0x04) #define BCM_DMA_INFO(n) (0x100*(n) + 0x08) #define INFO_INT_EN (1 << 0) Modified: stable/10/sys/arm/econa/if_ece.c ============================================================================== --- stable/10/sys/arm/econa/if_ece.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/econa/if_ece.c Tue Feb 4 03:36:42 2014 (r261455) @@ -1243,7 +1243,7 @@ configure_cpu_port(struct ece_softc *sc) /* SA learning Disable */ cpu_port_config |= (SA_LEARNING_DISABLE); /* set data offset + 2 */ - cpu_port_config &= ~(1 << 31); + cpu_port_config &= ~(1U << 31); write_4(sc, CPU_PORT_CONFIG, cpu_port_config); Modified: stable/10/sys/arm/freescale/imx/imx6_anatopreg.h ============================================================================== --- stable/10/sys/arm/freescale/imx/imx6_anatopreg.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/freescale/imx/imx6_anatopreg.h Tue Feb 4 03:36:42 2014 (r261455) @@ -37,7 +37,7 @@ #define IMX6_ANALOG_CCM_PLL_USB1_SET 0x014 #define IMX6_ANALOG_CCM_PLL_USB1_CLR 0x018 #define IMX6_ANALOG_CCM_PLL_USB1_TOG 0x01C -#define IMX6_ANALOG_CCM_PLL_USB_LOCK (1 << 31) +#define IMX6_ANALOG_CCM_PLL_USB_LOCK (1U << 31) #define IMX6_ANALOG_CCM_PLL_USB_BYPASS (1 << 16) #define IMX6_ANALOG_CCM_PLL_USB_ENABLE (1 << 13) #define IMX6_ANALOG_CCM_PLL_USB_POWER (1 << 12) Modified: stable/10/sys/arm/freescale/imx/imx6_usbphy.c ============================================================================== --- stable/10/sys/arm/freescale/imx/imx6_usbphy.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/freescale/imx/imx6_usbphy.c Tue Feb 4 03:36:42 2014 (r261455) @@ -57,7 +57,7 @@ __FBSDID("$FreeBSD$"); #define CTRL_SET_REG 0x0034 #define CTRL_CLR_REG 0x0038 #define CTRL_TOGGLE_REG 0x003c -#define CTRL_SFTRST (1 << 31) +#define CTRL_SFTRST (1U << 31) #define CTRL_CLKGATE (1 << 30) #define CTRL_ENUTMILEVEL3 (1 << 15) #define CTRL_ENUTMILEVEL2 (1 << 14) Modified: stable/10/sys/arm/freescale/imx/imx_gptreg.h ============================================================================== --- stable/10/sys/arm/freescale/imx/imx_gptreg.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/freescale/imx/imx_gptreg.h Tue Feb 4 03:36:42 2014 (r261455) @@ -32,7 +32,7 @@ /* Registers definition for Freescale i.MX515 Generic Periodic Timer */ #define IMX_GPT_CR 0x0000 /* Control Register R/W */ -#define GPT_CR_FO3 (1 << 31) +#define GPT_CR_FO3 (1U << 31) #define GPT_CR_FO2 (1 << 30) #define GPT_CR_FO1 (1 << 29) #define GPT_CR_OM3_SHIFT 26 Modified: stable/10/sys/arm/include/armreg.h ============================================================================== --- stable/10/sys/arm/include/armreg.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/include/armreg.h Tue Feb 4 03:36:42 2014 (r261455) @@ -363,7 +363,7 @@ #define CPU_CT_ARMV7 0x4 /* ARM v7 Cache type definitions */ -#define CPUV7_CT_CTYPE_WT (1 << 31) +#define CPUV7_CT_CTYPE_WT (1U << 31) #define CPUV7_CT_CTYPE_WB (1 << 30) #define CPUV7_CT_CTYPE_RA (1 << 29) #define CPUV7_CT_CTYPE_WA (1 << 28) Modified: stable/10/sys/arm/lpc/if_lpereg.h ============================================================================== --- stable/10/sys/arm/lpc/if_lpereg.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/lpc/if_lpereg.h Tue Feb 4 03:36:42 2014 (r261455) @@ -169,7 +169,7 @@ struct lpe_hwstatus { /* These are valid for both Rx and Tx descriptors */ #define LPE_HWDESC_SIZE_MASK (1 << 10) -#define LPE_HWDESC_INTERRUPT (1 << 31) +#define LPE_HWDESC_INTERRUPT (1U << 31) /* These are valid for Tx descriptors */ #define LPE_HWDESC_LAST (1 << 30) @@ -186,7 +186,7 @@ struct lpe_hwstatus { #define LPE_HWDESC_LATECOLL (1 << 28) #define LPE_HWDESC_UNDERRUN (1 << 29) #define LPE_HWDESC_TXNODESCR (1 << 30) -#define LPE_HWDESC_ERROR (1 << 31) +#define LPE_HWDESC_ERROR (1U << 31) /* These are valid for Rx status descriptors */ #define LPE_HWDESC_CONTROL (1 << 18) @@ -202,7 +202,7 @@ struct lpe_hwstatus { #define LPE_HWDESC_OVERRUN (1 << 28) #define LPE_HWDESC_RXNODESCR (1 << 29) #define LPE_HWDESC_LASTFLAG (1 << 30) -#define LPE_HWDESC_ERROR (1 << 31) +#define LPE_HWDESC_ERROR (1U << 31) #endif /* _ARM_LPC_IF_LPEREG_H */ Modified: stable/10/sys/arm/lpc/lpcreg.h ============================================================================== --- stable/10/sys/arm/lpc/lpcreg.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/lpc/lpcreg.h Tue Feb 4 03:36:42 2014 (r261455) @@ -604,7 +604,7 @@ #define LPC_DMAC_CH_LLI 0x08 #define LPC_DMAC_CH_LLI_AHB1 (1 << 0) #define LPC_DMAC_CH_CONTROL 0x0c -#define LPC_DMAC_CH_CONTROL_I (1 << 31) +#define LPC_DMAC_CH_CONTROL_I (1U << 31) #define LPC_DMAC_CH_CONTROL_DI (1 << 27) #define LPC_DMAC_CH_CONTROL_SI (1 << 26) #define LPC_DMAC_CH_CONTROL_D (1 << 25) Modified: stable/10/sys/arm/mv/mv_pci.c ============================================================================== --- stable/10/sys/arm/mv/mv_pci.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/mv/mv_pci.c Tue Feb 4 03:36:42 2014 (r261455) @@ -81,7 +81,7 @@ __FBSDID("$FreeBSD$"); #define debugf(fmt, args...) #endif -#define PCI_CFG_ENA (1 << 31) +#define PCI_CFG_ENA (1U << 31) #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) Modified: stable/10/sys/arm/samsung/exynos/ehci_exynos5.c ============================================================================== --- stable/10/sys/arm/samsung/exynos/ehci_exynos5.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/samsung/exynos/ehci_exynos5.c Tue Feb 4 03:36:42 2014 (r261455) @@ -82,7 +82,7 @@ __FBSDID("$FreeBSD$"); #define HOST_CTRL_SUSPEND (1 << 4) #define HOST_CTRL_RESET_LINK (1 << 1) #define HOST_CTRL_RESET_PHY (1 << 0) -#define HOST_CTRL_RESET_PHY_ALL (1 << 31) +#define HOST_CTRL_RESET_PHY_ALL (1U << 31) /* Forward declarations */ static int exynos_ehci_attach(device_t dev); Modified: stable/10/sys/arm/xscale/i8134x/i81342reg.h ============================================================================== --- stable/10/sys/arm/xscale/i8134x/i81342reg.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/xscale/i8134x/i81342reg.h Tue Feb 4 03:36:42 2014 (r261455) @@ -83,7 +83,7 @@ #define IOP34X_ADMA_PQTE (1 << 18) /* P+Q Transfer Enable */ #define IOP34X_ADMA_PTD (1 << 19) /* P Transfer Disable */ #define IOP34X_ADMA_ROE (1 << 30) /* Relaxed Ordering Enable */ -#define IOP34X_ADMA_NSE (1 << 31) /* No Snoop Enable */ +#define IOP34X_ADMA_NSE (1U << 31) /* No Snoop Enable */ #define IOP34X_PBBAR0 0x81588 /* PBI Base Address Register 0 */ #define IOP34X_PBBAR0_ADDRMASK 0xfffff000 @@ -113,7 +113,7 @@ #define SMC_SDBR 0x8180c /* Base Register */ #define SMC_SDBR_BASEADDR (1 << 27) #define SMC_SDBR_BASEADDR_MASK ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \ - | (1 << 31)) + | (1U << 31)) #define SMC_SDUBR 0x81810 /* Upper Base Register */ #define SMC_SBSR 0x81814 /* SDRAM Bank Size Register */ #define SMC_SBSR_BANK_NB (1 << 2) /* Number of DDR Banks @@ -128,7 +128,7 @@ 0x01000 1GB */ #define SMC_SBSR_BANK_SZ_MASK ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \ - | (1 << 31)) + | (1U << 31)) /* Two possible addresses for ATUe depending on configuration. */ @@ -190,7 +190,7 @@ #define ATU_CR_OUT_EN (1 << 1) #define ATU_PCSR 0x0074 /* PCI Configuration and Status Register */ #define PCIE_BUSNO(x) ((x & 0xff000000) >> 24) -#define ATUX_CORE_RST ((1 << 30) | (1 << 31)) /* Core Processor Reset */ +#define ATUX_CORE_RST ((1 << 30) | (1U << 31)) /* Core Processor Reset */ #define ATUX_P_RSTOUT (1 << 21) /* Central Resource PCI Bus Reset */ #define ATUE_CORE_RST ((1 << 9) | (1 << 8)) /* Core Processor Reset */ #define ATU_ISR 0x0078 /* ATU Interrupt Status Register */ @@ -250,7 +250,7 @@ #define ATU_OIOWTVR 0x0304 /* Outbound I/O Window Translate Value Reg */ #define ATU_OUMBAR0 0x0308 /* Outbound Upper Memory Window base addr reg 0*/ #define ATU_OUMBAR_FUNC (28) -#define ATU_OUMBAR_EN (1 << 31) +#define ATU_OUMBAR_EN (1U << 31) #define ATU_OUMWTVR0 0x030c /* Outbound Upper 32bit Memory Window Translate Value Register 0 */ #define ATU_OUMBAR1 0x0310 /* Outbound Upper Memory Window base addr reg1*/ #define ATU_OUMWTVR1 0x0314 /* Outbound Upper 32bit Memory Window Translate Value Register 1 */ Modified: stable/10/sys/arm/xscale/ixp425/ixp425reg.h ============================================================================== --- stable/10/sys/arm/xscale/ixp425/ixp425reg.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/arm/xscale/ixp425/ixp425reg.h Tue Feb 4 03:36:42 2014 (r261455) @@ -400,7 +400,7 @@ #define EXP_CNFG0_PCI_HOST (1 << 1) #define EXP_CNFG0_PCI_ARB (1 << 2) #define EXP_CNFG0_PCI_66MHZ (1 << 4) -#define EXP_CNFG0_MEM_MAP (1 << 31) +#define EXP_CNFG0_MEM_MAP (1U << 31) /* EXP_CNFG1 bits */ #define EXP_CNFG1_SW_INT0 (1 << 0) Modified: stable/10/sys/boot/arm/at91/libat91/mci_device.h ============================================================================== --- stable/10/sys/boot/arm/at91/libat91/mci_device.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/boot/arm/at91/libat91/mci_device.h Tue Feb 4 03:36:42 2014 (r261455) @@ -306,7 +306,7 @@ typedef struct _AT91S_MciDevice #define AT91C_VDD_33_34 (1 << 21) #define AT91C_VDD_34_35 (1 << 22) #define AT91C_VDD_35_36 (1 << 23) -#define AT91C_CARD_POWER_UP_BUSY (1 << 31) +#define AT91C_CARD_POWER_UP_BUSY (1U << 31) #define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 | AT91C_VDD_28_29 | \ AT91C_VDD_29_30 | AT91C_VDD_30_31 | AT91C_VDD_31_32 | AT91C_VDD_32_33) Modified: stable/10/sys/boot/i386/libfirewire/fwohci.h ============================================================================== --- stable/10/sys/boot/i386/libfirewire/fwohci.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/boot/i386/libfirewire/fwohci.h Tue Feb 4 03:36:42 2014 (r261455) @@ -76,7 +76,7 @@ void fwohci_poll(struct fwohci_softc *); #define OHCI_CROMHDR 0x18 #define OHCI_BUS_ID 0x1c #define OHCI_BUS_OPT 0x20 -#define OHCI_BUSIRMC (1 << 31) +#define OHCI_BUSIRMC (1U << 31) #define OHCI_BUSCMC (1 << 30) #define OHCI_BUSISC (1 << 29) #define OHCI_BUSBMC (1 << 28) @@ -102,7 +102,7 @@ void fwohci_poll(struct fwohci_softc *); #define OHCI_SID_BUF 0x64 #define OHCI_SID_CNT 0x68 -#define OHCI_SID_ERR (1 << 31) +#define OHCI_SID_ERR (1U << 31) #define OHCI_SID_CNT_MASK 0xffc #define OHCI_IT_STAT 0x90 Modified: stable/10/sys/boot/i386/libfirewire/fwohcireg.h ============================================================================== --- stable/10/sys/boot/i386/libfirewire/fwohcireg.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/boot/i386/libfirewire/fwohcireg.h Tue Feb 4 03:36:42 2014 (r261455) @@ -239,7 +239,7 @@ struct ohci_registers { fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ -#define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */ +#define OHCI_HCC_BIBIV (1U << 31) /* BIBimage Valid */ #define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */ #define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */ #define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */ @@ -278,7 +278,7 @@ struct ohci_registers { fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ #define FWOHCI_NODEID 0xe8 fwohcireg_t node; /* Node ID 0xe8 */ -#define OHCI_NODE_VALID (1 << 31) +#define OHCI_NODE_VALID (1U << 31) #define OHCI_NODE_ROOT (1 << 30) #define OHCI_ASYSRCBUS 1 Modified: stable/10/sys/dev/aac/aacvar.h ============================================================================== --- stable/10/sys/dev/aac/aacvar.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/aac/aacvar.h Tue Feb 4 03:36:42 2014 (r261455) @@ -412,7 +412,7 @@ struct aac_softc #define AAC_FLAGS_RAW_IO (1 << 12) /* Raw I/O interface */ #define AAC_FLAGS_ARRAY_64BIT (1 << 13) /* 64-bit array size */ #define AAC_FLAGS_LBA_64BIT (1 << 14) /* 64-bit LBA support */ -#define AAC_FLAGS_NOMSI (1 << 31) /* Broken MSI */ +#define AAC_FLAGS_NOMSI (1U << 31) /* Broken MSI */ u_int32_t supported_options; u_int32_t scsi_method_id; Modified: stable/10/sys/dev/acpica/acpi_video.c ============================================================================== --- stable/10/sys/dev/acpica/acpi_video.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/acpica/acpi_video.c Tue Feb 4 03:36:42 2014 (r261455) @@ -132,7 +132,7 @@ static void vo_set_device_state(ACPI_HAN #define DOD_HEAD_ID_BITS 3 #define DOD_HEAD_ID_MASK \ (((1 << DOD_HEAD_ID_BITS) - 1) << DOD_HEAD_ID_SHIFT) -#define DOD_DEVID_SCHEME_STD (1 << 31) +#define DOD_DEVID_SCHEME_STD (1U << 31) /* _BCL related constants */ #define BCL_FULLPOWER 0 @@ -149,7 +149,7 @@ static void vo_set_device_state(ACPI_HAN #define DSS_INACTIVE 0 #define DSS_ACTIVE (1 << 0) #define DSS_SETNEXT (1 << 30) -#define DSS_COMMIT (1 << 31) +#define DSS_COMMIT (1U << 31) static device_method_t acpi_video_methods[] = { DEVMETHOD(device_identify, acpi_video_identify), Modified: stable/10/sys/dev/agp/agp_i810.c ============================================================================== --- stable/10/sys/dev/agp/agp_i810.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/agp/agp_i810.c Tue Feb 4 03:36:42 2014 (r261455) @@ -2226,10 +2226,10 @@ agp_i830_chipset_flush(device_t dev) sc = device_get_softc(dev); pmap_invalidate_cache(); hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC); - bus_write_4(sc->sc_res[0], AGP_I830_HIC, hic | (1 << 31)); + bus_write_4(sc->sc_res[0], AGP_I830_HIC, hic | (1U << 31)); for (i = 0; i < 20000 /* 1 sec */; i++) { hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC); - if ((hic & (1 << 31)) == 0) + if ((hic & (1U << 31)) == 0) break; DELAY(50); } Modified: stable/10/sys/dev/ahci/ahci.h ============================================================================== --- stable/10/sys/dev/ahci/ahci.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/ahci/ahci.h Tue Feb 4 03:36:42 2014 (r261455) @@ -321,7 +321,7 @@ struct ahci_dma_prd { u_int32_t dbc; /* 0 based */ #define AHCI_PRD_MASK 0x003fffff /* max 4MB */ #define AHCI_PRD_MAX (AHCI_PRD_MASK + 1) -#define AHCI_PRD_IPC (1 << 31) +#define AHCI_PRD_IPC (1U << 31) } __packed; struct ahci_cmd_tab { Modified: stable/10/sys/dev/bktr/bktr_core.c ============================================================================== --- stable/10/sys/dev/bktr/bktr_core.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/bktr/bktr_core.c Tue Feb 4 03:36:42 2014 (r261455) @@ -2599,7 +2599,7 @@ dump_bt848( bktr_ptr_t bktr ) #define BKTR_TEST_RISC_STATUS_BIT0 (1 << 28) #define BKTR_TEST_RISC_STATUS_BIT1 (1 << 29) #define BKTR_TEST_RISC_STATUS_BIT2 (1 << 30) -#define BKTR_TEST_RISC_STATUS_BIT3 (1 << 31) +#define BKTR_TEST_RISC_STATUS_BIT3 (1U << 31) static bool_t notclipped (bktr_reg_t * bktr, int x, int width) { int i; Modified: stable/10/sys/dev/cesa/cesa.h ============================================================================== --- stable/10/sys/dev/cesa/cesa.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/cesa/cesa.h Tue Feb 4 03:36:42 2014 (r261455) @@ -297,8 +297,8 @@ struct cesa_chain_info { #define CESA_CSH_AES_KLEN_MASK (3 << 24) #define CESA_CSHD_FRAG_FIRST (1 << 30) -#define CESA_CSHD_FRAG_LAST (2 << 30) -#define CESA_CSHD_FRAG_MIDDLE (3 << 30) +#define CESA_CSHD_FRAG_LAST (2U << 30) +#define CESA_CSHD_FRAG_MIDDLE (3U << 30) /* CESA registers definitions */ #define CESA_ICR 0xDE20 Modified: stable/10/sys/dev/drm/i915_reg.h ============================================================================== --- stable/10/sys/dev/drm/i915_reg.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/drm/i915_reg.h Tue Feb 4 03:36:42 2014 (r261455) @@ -349,7 +349,7 @@ __FBSDID("$FreeBSD$"); #define VGA1_PD_P1_MASK (0x1f << 8) #define DPLL_A 0x06014 #define DPLL_B 0x06018 -#define DPLL_VCO_ENABLE (1 << 31) +#define DPLL_VCO_ENABLE (1U << 31) #define DPLL_DVO_HIGH_SPEED (1 << 30) #define DPLL_SYNCLOCK_ENABLE (1 << 29) #define DPLL_VGA_MODE_DIS (1 << 28) @@ -653,7 +653,7 @@ __FBSDID("$FreeBSD$"); /* SDVO port control */ #define SDVOB 0x61140 #define SDVOC 0x61160 -#define SDVO_ENABLE (1 << 31) +#define SDVO_ENABLE (1U << 31) #define SDVO_PIPE_B_SELECT (1 << 30) #define SDVO_STALL_SELECT (1 << 29) #define SDVO_INTERRUPT_ENABLE (1 << 26) @@ -690,7 +690,7 @@ __FBSDID("$FreeBSD$"); #define DVOA 0x61120 #define DVOB 0x61140 #define DVOC 0x61160 -#define DVO_ENABLE (1 << 31) +#define DVO_ENABLE (1U << 31) #define DVO_PIPE_B_SELECT (1 << 30) #define DVO_PIPE_STALL_UNUSED (0 << 28) #define DVO_PIPE_STALL (1 << 28) @@ -726,7 +726,7 @@ __FBSDID("$FreeBSD$"); * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ -#define LVDS_PORT_EN (1 << 31) +#define LVDS_PORT_EN (1U << 31) /* Selects pipe B for LVDS data. Must be set on pre-965. */ #define LVDS_PIPEB_SELECT (1 << 30) /* @@ -762,7 +762,7 @@ __FBSDID("$FreeBSD$"); /* Panel power sequencing */ #define PP_STATUS 0x61200 -#define PP_ON (1 << 31) +#define PP_ON (1U << 31) /* * Indicates that all dependencies of the panel are on: * @@ -783,7 +783,7 @@ __FBSDID("$FreeBSD$"); /* Panel fitting */ #define PFIT_CONTROL 0x61230 -#define PFIT_ENABLE (1 << 31) +#define PFIT_ENABLE (1U << 31) #define PFIT_PIPE_MASK (3 << 29) #define PFIT_PIPE_SHIFT 29 #define VERT_INTERP_DISABLE (0 << 10) @@ -826,7 +826,7 @@ __FBSDID("$FreeBSD$"); /* TV port control */ #define TV_CTL 0x68000 /** Enables the TV encoder */ -# define TV_ENC_ENABLE (1 << 31) +# define TV_ENC_ENABLE (1U << 31) /** Sources the TV encoder input from pipe B instead of A. */ # define TV_ENC_PIPEB_SELECT (1 << 30) /** Outputs composite video (DAC A only) */ @@ -897,7 +897,7 @@ __FBSDID("$FreeBSD$"); * * This gets cleared when TV_DAC_STATE_EN is cleared */ -# define TVDAC_STATE_CHG (1 << 31) +# define TVDAC_STATE_CHG (1U << 31) # define TVDAC_SENSE_MASK (7 << 28) /** Reports that DAC A voltage is above the detect threshold */ # define TVDAC_A_SENSE (1 << 30) @@ -1024,7 +1024,7 @@ __FBSDID("$FreeBSD$"); #define TV_H_CTL_2 0x68034 /** Enables the colorburst (needed for non-component color) */ -# define TV_BURST_ENA (1 << 31) +# define TV_BURST_ENA (1U << 31) /** Offset of the colorburst from the start of hsync, in pixels minus one. */ # define TV_HBURST_START_SHIFT 16 # define TV_HBURST_START_MASK 0x1fff0000 @@ -1069,7 +1069,7 @@ __FBSDID("$FreeBSD$"); #define TV_V_CTL_3 0x68044 /** Enables generation of the equalization signal */ -# define TV_EQUAL_ENA (1 << 31) +# define TV_EQUAL_ENA (1U << 31) /** Length of vsync, in half lines */ # define TV_VEQ_LEN_MASK 0x007f0000 # define TV_VEQ_LEN_SHIFT 16 @@ -1143,7 +1143,7 @@ __FBSDID("$FreeBSD$"); #define TV_SC_CTL_1 0x68060 /** Turns on the first subcarrier phase generation DDA */ -# define TV_SC_DDA1_EN (1 << 31) +# define TV_SC_DDA1_EN (1U << 31) /** Turns on the first subcarrier phase generation DDA */ # define TV_SC_DDA2_EN (1 << 30) /** Turns on the first subcarrier phase generation DDA */ @@ -1206,7 +1206,7 @@ __FBSDID("$FreeBSD$"); * If set, the rest of the registers are ignored, and the calculated values can * be read back from the register. */ -# define TV_AUTO_SCALE (1 << 31) +# define TV_AUTO_SCALE (1U << 31) /** * Disables the vertical filter. * @@ -1269,7 +1269,7 @@ __FBSDID("$FreeBSD$"); # define TV_VSCALE_IP_FRAC_SHIFT 0 #define TV_CC_CONTROL 0x68090 -# define TV_CC_ENABLE (1 << 31) +# define TV_CC_ENABLE (1U << 31) /** * Specifies which field to send the CC data in. * @@ -1285,7 +1285,7 @@ __FBSDID("$FreeBSD$"); # define TV_CC_LINE_SHIFT 0 #define TV_CC_DATA 0x68094 -# define TV_CC_RDY (1 << 31) +# define TV_CC_RDY (1U << 31) /** Second word of CC data to be transmitted. */ # define TV_CC_DATA_2_MASK 0x007f0000 # define TV_CC_DATA_2_SHIFT 16 @@ -1469,7 +1469,7 @@ __FBSDID("$FreeBSD$"); /* VBIOS regs */ #define VGACNTRL 0x71400 -# define VGA_DISP_DISABLE (1 << 31) +# define VGA_DISP_DISABLE (1U << 31) # define VGA_2X_MODE (1 << 30) # define VGA_PIPE_B_SELECT (1 << 29) Modified: stable/10/sys/dev/drm/mach64_drv.h ============================================================================== --- stable/10/sys/dev/drm/mach64_drv.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/drm/mach64_drv.h Tue Feb 4 03:36:42 2014 (r261455) @@ -202,7 +202,7 @@ extern void mach64_driver_irq_uninstall( # define MACH64_CIRCULAR_BUF_SIZE_32KB (1 << 0) # define MACH64_CIRCULAR_BUF_SIZE_64KB (2 << 0) # define MACH64_CIRCULAR_BUF_SIZE_128KB (3 << 0) -# define MACH64_LAST_DESCRIPTOR (1 << 31) +# define MACH64_LAST_DESCRIPTOR (1U << 31) #define MACH64_BM_HOSTDATA 0x0644 #define MACH64_BM_STATUS 0x018c #define MACH64_BM_SYSTEM_MEM_ADDR 0x0184 @@ -316,7 +316,7 @@ extern void mach64_driver_irq_uninstall( #define MACH64_FIFO_STAT 0x0710 # define MACH64_FIFO_SLOT_MASK 0x0000ffff -# define MACH64_FIFO_ERR (1 << 31) +# define MACH64_FIFO_ERR (1U << 31) #define MACH64_GEN_TEST_CNTL 0x04d0 # define MACH64_GUI_ENGINE_ENABLE (1 << 8) @@ -442,7 +442,7 @@ extern void mach64_driver_irq_uninstall( # define MACH64_CRTC2_VLINE_SYNC (1 << 28) /* LT Pro */ /* 0=even, 1=odd */ # define MACH64_CRTC_SNAPSHOT2_INT_EN (1 << 29) /* LT Pro */ # define MACH64_CRTC_SNAPSHOT2_INT (1 << 30) /* LT Pro */ -# define MACH64_CRTC_VBLANK2_INT (1 << 31) +# define MACH64_CRTC_VBLANK2_INT (1U << 31) # define MACH64_CRTC_INT_ENS \ ( \ MACH64_CRTC_VBLANK_INT_EN | \ Modified: stable/10/sys/dev/drm/mga_drv.h ============================================================================== --- stable/10/sys/dev/drm/mga_drv.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/drm/mga_drv.h Tue Feb 4 03:36:42 2014 (r261455) @@ -458,7 +458,7 @@ do { \ # define MGA_BLTMOD_BU24RGB (15 << 25) # define MGA_PATTERN (1 << 29) # define MGA_TRANSC (1 << 30) -# define MGA_CLIPDIS (1 << 31) +# define MGA_CLIPDIS (1U << 31) #define MGA_DWGSYNC 0x2c4c #define MGA_FCOL 0x1c24 @@ -526,7 +526,7 @@ do { \ #define MGA_TEXCTL2 0x2c3c # define MGA_DUALTEX (1 << 7) # define MGA_G400_TC2_MAGIC (1 << 15) -# define MGA_MAP1_ENABLE (1 << 31) +# define MGA_MAP1_ENABLE (1U << 31) #define MGA_TEXFILTER 0x2c58 #define MGA_TEXHEIGHT 0x2c2c #define MGA_TEXORG 0x2c24 Modified: stable/10/sys/dev/drm/r128_drv.h ============================================================================== --- stable/10/sys/dev/drm/r128_drv.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/drm/r128_drv.h Tue Feb 4 03:36:42 2014 (r261455) @@ -227,7 +227,7 @@ extern long r128_compat_ioctl(struct fil # define R128_ROP3_P 0x00f00000 #define R128_DP_WRITE_MASK 0x16cc #define R128_DST_PITCH_OFFSET_C 0x1c80 -# define R128_DST_TILE (1 << 31) +# define R128_DST_TILE (1U << 31) #define R128_GEN_INT_CNTL 0x0040 # define R128_CRTC_VBLANK_INT_EN (1 << 0) @@ -246,7 +246,7 @@ extern long r128_compat_ioctl(struct fil #define R128_GUI_STAT 0x1740 # define R128_GUI_FIFOCNT_MASK 0x0fff -# define R128_GUI_ACTIVE (1 << 31) +# define R128_GUI_ACTIVE (1U << 31) #define R128_MCLK_CNTL 0x000f # define R128_FORCE_GCP (1 << 16) @@ -258,7 +258,7 @@ extern long r128_compat_ioctl(struct fil # define R128_PC_FLUSH_GUI (3 << 0) # define R128_PC_RI_GUI (1 << 2) # define R128_PC_FLUSH_ALL 0x00ff -# define R128_PC_BUSY (1 << 31) +# define R128_PC_BUSY (1U << 31) #define R128_PCI_GART_PAGE 0x017c #define R128_PRIM_TEX_CNTL_C 0x1cb0 @@ -302,7 +302,7 @@ extern long r128_compat_ioctl(struct fil #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c #define R128_PM4_BUFFER_DL_RPTR 0x0710 #define R128_PM4_BUFFER_DL_WPTR 0x0714 -# define R128_PM4_BUFFER_DL_DONE (1 << 31) +# define R128_PM4_BUFFER_DL_DONE (1U << 31) #define R128_PM4_VC_FPU_SETUP 0x071c @@ -312,7 +312,7 @@ extern long r128_compat_ioctl(struct fil #define R128_PM4_STAT 0x07b8 # define R128_PM4_FIFOCNT_MASK 0x0fff # define R128_PM4_BUSY (1 << 16) -# define R128_PM4_GUI_ACTIVE (1 << 31) +# define R128_PM4_GUI_ACTIVE (1U << 31) #define R128_PM4_MICROCODE_ADDR 0x07d4 #define R128_PM4_MICROCODE_RADDR 0x07d8 Modified: stable/10/sys/dev/drm/r300_reg.h ============================================================================== --- stable/10/sys/dev/drm/r300_reg.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/drm/r300_reg.h Tue Feb 4 03:36:42 2014 (r261455) @@ -1205,7 +1205,7 @@ __FBSDID("$FreeBSD$"); # define R300_FPI0_OUTC_FRC (9 << 23) # define R300_FPI0_OUTC_REPL_ALPHA (10 << 23) # define R300_FPI0_OUTC_SAT (1 << 30) -# define R300_FPI0_INSERT_NOP (1 << 31) +# define R300_FPI0_INSERT_NOP (1U << 31) #define R300_PFS_INSTR2_0 0x49C0 # define R300_FPI2_ARGA_SRC0C_X 0 @@ -1252,7 +1252,7 @@ __FBSDID("$FreeBSD$"); # define R300_FPI2_OUTA_RCP (10 << 23) # define R300_FPI2_OUTA_RSQ (11 << 23) # define R300_FPI2_OUTA_SAT (1 << 30) -# define R300_FPI2_UNKNOWN_31 (1 << 31) +# define R300_FPI2_UNKNOWN_31 (1U << 31) /* END: Fragment program instruction set */ /* Fog state and color */ @@ -1452,7 +1452,7 @@ __FBSDID("$FreeBSD$"); # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1) # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1) # define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31) -# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31) +# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1U << 31) #define R300_ZB_BW_CNTL 0x4f1c # define R300_HIZ_DISABLE (0 << 0) Modified: stable/10/sys/dev/drm/r600_blit.c ============================================================================== --- stable/10/sys/dev/drm/r600_blit.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/drm/r600_blit.c Tue Feb 4 03:36:42 2014 (r261455) @@ -1428,12 +1428,12 @@ set_scissors(drm_radeon_private_t *dev_p OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); - OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); + OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31)); OUT_RING((x2 << 0) | (y2 << 16)); OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2)); OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2); - OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31)); + OUT_RING((x1 << 0) | (y1 << 16) | (1U << 31)); OUT_RING((x2 << 0) | (y2 << 16)); ADVANCE_RING(); } Modified: stable/10/sys/dev/drm/radeon_cp.c ============================================================================== --- stable/10/sys/dev/drm/radeon_cp.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/drm/radeon_cp.c Tue Feb 4 03:36:42 2014 (r261455) @@ -542,7 +542,7 @@ static void radeon_do_cp_flush(drm_radeo #if 0 u32 tmp; - tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); + tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1U << 31); RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); #endif } Modified: stable/10/sys/dev/drm/radeon_drv.h ============================================================================== --- stable/10/sys/dev/drm/radeon_drv.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/drm/radeon_drv.h Tue Feb 4 03:36:42 2014 (r261455) @@ -659,7 +659,7 @@ extern int r600_cs_init(struct drm_devic # define RS480_GTW_LAC_EN (1 << 25) # define RS480_2LEVEL_GART (0 << 30) # define RS480_1LEVEL_GART (1 << 30) -# define RS480_PDC_EN (1 << 31) +# define RS480_PDC_EN (1U << 31) #define RS480_GART_BASE 0x2c #define RS480_GART_CACHE_CNTRL 0x2e # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ @@ -775,7 +775,7 @@ extern int r600_cs_init(struct drm_devic # define R300_SUBPIXEL_1_12 (0 << 16) # define R300_SUBPIXEL_1_16 (1 << 16) #define R300_DST_PIPE_CONFIG 0x170c -# define R300_PIPE_AUTO_CONFIG (1 << 31) +# define R300_PIPE_AUTO_CONFIG (1U << 31) #define R300_RB2D_DSTCACHE_MODE 0x3428 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) @@ -807,8 +807,8 @@ extern int r600_cs_init(struct drm_devic #define RADEON_DST_PITCH_OFFSET_C 0x1c80 # define RADEON_DST_TILE_LINEAR (0 << 30) # define RADEON_DST_TILE_MACRO (1 << 30) -# define RADEON_DST_TILE_MICRO (2 << 30) -# define RADEON_DST_TILE_BOTH (3 << 30) +# define RADEON_DST_TILE_MICRO (2U << 30) +# define RADEON_DST_TILE_BOTH (3U << 30) #define RADEON_SCRATCH_REG0 0x15e0 #define RADEON_SCRATCH_REG1 0x15e4 @@ -902,7 +902,7 @@ extern u32 radeon_get_scratch(drm_radeon # define R300_RB2D_DC_FLUSH (3 << 0) # define R300_RB2D_DC_FREE (3 << 2) # define R300_RB2D_DC_FLUSH_ALL 0xf -# define R300_RB2D_DC_BUSY (1 << 31) +# define R300_RB2D_DC_BUSY (1U << 31) #define RADEON_RB3D_CNTL 0x1c3c # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) # define RADEON_PLANE_MASK_ENABLE (1 << 1) @@ -924,16 +924,16 @@ extern u32 radeon_get_scratch(drm_radeon # define RADEON_RB3D_ZC_FLUSH (1 << 0) # define RADEON_RB3D_ZC_FREE (1 << 2) # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 -# define RADEON_RB3D_ZC_BUSY (1 << 31) +# define RADEON_RB3D_ZC_BUSY (1U << 31) #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 # define R300_ZC_FLUSH (1 << 0) # define R300_ZC_FREE (1 << 1) -# define R300_ZC_BUSY (1 << 31) +# define R300_ZC_BUSY (1U << 31) #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c # define RADEON_RB3D_DC_FLUSH (3 << 0) # define RADEON_RB3D_DC_FREE (3 << 2) # define RADEON_RB3D_DC_FLUSH_ALL 0xf -# define RADEON_RB3D_DC_BUSY (1 << 31) +# define RADEON_RB3D_DC_BUSY (1U << 31) #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c # define R300_RB3D_DC_FLUSH (2 << 0) # define R300_RB3D_DC_FREE (2 << 2) @@ -949,7 +949,7 @@ extern u32 radeon_get_scratch(drm_radeon # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) # define RADEON_FORCE_Z_DIRTY (1 << 29) # define RADEON_Z_WRITE_ENABLE (1 << 30) -# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) +# define RADEON_Z_DECOMPRESSION_ENABLE (1U << 31) #define RADEON_RBBM_SOFT_RESET 0x00f0 # define RADEON_SOFT_RESET_CP (1 << 0) # define RADEON_SOFT_RESET_HI (1 << 1) @@ -1003,7 +1003,7 @@ extern u32 radeon_get_scratch(drm_radeon # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ # define RADEON_GA_BUSY (1 << 26) # define RADEON_CBA2D_BUSY (1 << 27) -# define RADEON_RBBM_ACTIVE (1 << 31) +# define RADEON_RBBM_ACTIVE (1U << 31) #define RADEON_RE_LINE_PATTERN 0x1cd0 #define RADEON_RE_MISC 0x26c4 #define RADEON_RE_TOP_LEFT 0x26c0 @@ -1117,7 +1117,7 @@ extern u32 radeon_get_scratch(drm_radeon #define RADEON_CP_RB_CNTL 0x0704 # define RADEON_BUF_SWAP_32BIT (2 << 16) # define RADEON_RB_NO_UPDATE (1 << 27) -# define RADEON_RB_RPTR_WR_ENA (1 << 31) +# define RADEON_RB_RPTR_WR_ENA (1U << 31) #define RADEON_CP_RB_RPTR_ADDR 0x070c #define RADEON_CP_RB_RPTR 0x0710 #define RADEON_CP_RB_WPTR 0x0714 @@ -1193,7 +1193,7 @@ extern u32 radeon_get_scratch(drm_radeon #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 -#define RADEON_VTX_Z_PRESENT (1 << 31) +#define RADEON_VTX_Z_PRESENT (1U << 31) #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) #define RADEON_PRIM_TYPE_NONE (0 << 0) @@ -1524,7 +1524,7 @@ extern u32 radeon_get_scratch(drm_radeon #define R600_GRBM_STATUS 0x8010 # define R600_CMDFIFO_AVAIL_MASK 0x1f # define R700_CMDFIFO_AVAIL_MASK 0xf -# define R600_GUI_ACTIVE (1 << 31) +# define R600_GUI_ACTIVE (1U << 31) #define R600_GRBM_STATUS2 0x8014 #define R600_GRBM_SOFT_RESET 0x8020 # define R600_SOFT_RESET_CP (1 << 0) @@ -1546,7 +1546,7 @@ extern u32 radeon_get_scratch(drm_radeon # define R600_RB_BUFSZ(x) ((x) << 0) # define R600_RB_BLKSZ(x) ((x) << 8) # define R600_RB_NO_UPDATE (1 << 27) -# define R600_RB_RPTR_WR_ENA (1 << 31) +# define R600_RB_RPTR_WR_ENA (1U << 31) #define R600_CP_RB_RPTR_WR 0xc108 #define R600_CP_RB_RPTR_ADDR 0xc10c #define R600_CP_RB_RPTR_ADDR_HI 0xc110 @@ -1619,7 +1619,7 @@ extern u32 radeon_get_scratch(drm_radeon #define R600_SX_MISC 0x28350 #define R600_DB_DEBUG 0x9830 -# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) +# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31) #define R600_DB_WATERMARKS 0x9838 # define R600_DEPTH_FREE(x) ((x) << 0) # define R600_DEPTH_FLUSH(x) ((x) << 5) @@ -1679,7 +1679,7 @@ extern u32 radeon_get_scratch(drm_radeon # define R600_SYNC_WALKER (1 << 25) # define R600_SYNC_ALIGNER (1 << 26) # define R600_BILINEAR_PRECISION_6_BIT (0 << 31) -# define R600_BILINEAR_PRECISION_8_BIT (1 << 31) +# define R600_BILINEAR_PRECISION_8_BIT (1U << 31) #define R700_TCP_CNTL 0x9610 @@ -1753,7 +1753,7 @@ extern u32 radeon_get_scratch(drm_radeon # define R600_PERSP_GRADIENT_ENA (1 << 28) # define R600_LINEAR_GRADIENT_ENA (1 << 29) # define R600_POSITION_SAMPLE (1 << 30) -# define R600_BARYC_AT_SAMPLE_ENA (1 << 31) +# define R600_BARYC_AT_SAMPLE_ENA (1U << 31) #define R600_SPI_PS_IN_CONTROL_1 0x286d0 # define R600_GEN_INDEX_PIX (1 << 0) # define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) Modified: stable/10/sys/dev/drm/via_irq.c ============================================================================== --- stable/10/sys/dev/drm/via_irq.c Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/drm/via_irq.c Tue Feb 4 03:36:42 2014 (r261455) @@ -46,7 +46,7 @@ __FBSDID("$FreeBSD$"); #define VIA_REG_INTERRUPT 0x200 /* VIA_REG_INTERRUPT */ -#define VIA_IRQ_GLOBAL (1 << 31) +#define VIA_IRQ_GLOBAL (1U << 31) #define VIA_IRQ_VBLANK_ENABLE (1 << 19) #define VIA_IRQ_VBLANK_PENDING (1 << 3) #define VIA_IRQ_HQV0_ENABLE (1 << 11) Modified: stable/10/sys/dev/drm2/i915/i915_reg.h ============================================================================== --- stable/10/sys/dev/drm2/i915/i915_reg.h Tue Feb 4 03:01:33 2014 (r261454) +++ stable/10/sys/dev/drm2/i915/i915_reg.h Tue Feb 4 03:36:42 2014 (r261455) @@ -798,7 +798,7 @@ __FBSDID("$FreeBSD$"); #define _DPLL_A 0x06014 #define _DPLL_B 0x06018 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) -#define DPLL_VCO_ENABLE (1 << 31) +#define DPLL_VCO_ENABLE (1U << 31) #define DPLL_DVO_HIGH_SPEED (1 << 30) #define DPLL_SYNCLOCK_ENABLE (1 << 29) #define DPLL_VGA_MODE_DIS (1 << 28) @@ -1483,7 +1483,7 @@ __FBSDID("$FreeBSD$"); /* SDVO port control */ #define SDVOB 0x61140 #define SDVOC 0x61160 -#define SDVO_ENABLE (1 << 31) +#define SDVO_ENABLE (1U << 31) #define SDVO_PIPE_B_SELECT (1 << 30) #define SDVO_STALL_SELECT (1 << 29) #define SDVO_INTERRUPT_ENABLE (1 << 26) @@ -1521,7 +1521,7 @@ __FBSDID("$FreeBSD$"); #define DVOA 0x61120 #define DVOB 0x61140 #define DVOC 0x61160 -#define DVO_ENABLE (1 << 31) +#define DVO_ENABLE (1U << 31) #define DVO_PIPE_B_SELECT (1 << 30) #define DVO_PIPE_STALL_UNUSED (0 << 28) #define DVO_PIPE_STALL (1 << 28) @@ -1557,7 +1557,7 @@ __FBSDID("$FreeBSD$"); * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ -#define LVDS_PORT_EN (1 << 31) +#define LVDS_PORT_EN (1U << 31) /* Selects pipe B for LVDS data. Must be set on pre-965. */ #define LVDS_PIPEB_SELECT (1 << 30) #define LVDS_PIPE_MASK (1 << 30) @@ -1604,7 +1604,7 @@ __FBSDID("$FreeBSD$"); /* Video Data Island Packet control */ #define VIDEO_DIP_DATA 0x61178 #define VIDEO_DIP_CTL 0x61170 -#define VIDEO_DIP_ENABLE (1 << 31) +#define VIDEO_DIP_ENABLE (1U << 31) #define VIDEO_DIP_PORT_B (1 << 29) #define VIDEO_DIP_PORT_C (2 << 29) #define VIDEO_DIP_ENABLE_AVI (1 << 21) @@ -1620,7 +1620,7 @@ __FBSDID("$FreeBSD$"); /* Panel power sequencing */ #define PP_STATUS 0x61200 -#define PP_ON (1 << 31) +#define PP_ON (1U << 31) /* * Indicates that all dependencies of the panel are on: * @@ -1653,7 +1653,7 @@ __FBSDID("$FreeBSD$"); /* Panel fitting */ #define PFIT_CONTROL 0x61230 -#define PFIT_ENABLE (1 << 31) +#define PFIT_ENABLE (1U << 31) #define PFIT_PIPE_MASK (3 << 29) #define PFIT_PIPE_SHIFT 29 #define VERT_INTERP_DISABLE (0 << 10) @@ -1714,7 +1714,7 @@ __FBSDID("$FreeBSD$"); /* TV port control */ #define TV_CTL 0x68000 /** Enables the TV encoder */ -# define TV_ENC_ENABLE (1 << 31) +# define TV_ENC_ENABLE (1U << 31) /** Sources the TV encoder input from pipe B instead of A. */ # define TV_ENC_PIPEB_SELECT (1 << 30) /** Outputs composite video (DAC A only) */ @@ -1786,7 +1786,7 @@ __FBSDID("$FreeBSD$"); * * This gets cleared when TV_DAC_STATE_EN is cleared */ -# define TVDAC_STATE_CHG (1 << 31) +# define TVDAC_STATE_CHG (1U << 31) # define TVDAC_SENSE_MASK (7 << 28) /** Reports that DAC A voltage is above the detect threshold */ # define TVDAC_A_SENSE (1 << 30) @@ -1913,7 +1913,7 @@ __FBSDID("$FreeBSD$"); #define TV_H_CTL_2 0x68034 /** Enables the colorburst (needed for non-component color) */ -# define TV_BURST_ENA (1 << 31) +# define TV_BURST_ENA (1U << 31) /** Offset of the colorburst from the start of hsync, in pixels minus one. */ # define TV_HBURST_START_SHIFT 16 # define TV_HBURST_START_MASK 0x1fff0000 *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***