Date: Sun, 21 Oct 2007 04:00:09 GMT From: Kip Macy <kmacy@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 127877 for review Message-ID: <200710210400.l9L409ai002604@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=127877 Change 127877 by kmacy@kmacy_home:ethng on 2007/10/21 04:00:00 add remaining iw_cxgb3 driver bits and shim in genalloc api Affected files ... .. //depot/projects/ethng/src/sys/dev/cxgb/cxgb_osdep.h#16 edit .. //depot/projects/ethng/src/sys/dev/cxgb/sys/cxgb_support.c#5 edit .. //depot/projects/ethng/src/sys/dev/cxgb/ulp/iw_cxgb/iw_cxgb_cxio_dbg.c#1 add .. //depot/projects/ethng/src/sys/dev/cxgb/ulp/iw_cxgb/iw_cxgb_cxio_hal.h#4 edit .. //depot/projects/ethng/src/sys/dev/cxgb/ulp/iw_cxgb/iw_cxgb_cxio_resource.c#1 add .. //depot/projects/ethng/src/sys/dev/cxgb/ulp/iw_cxgb/iw_cxgb_iwch_cq.c#1 add .. //depot/projects/ethng/src/sys/dev/cxgb/ulp/iw_cxgb/iw_cxgb_iwch_ev.c#1 add .. //depot/projects/ethng/src/sys/dev/cxgb/ulp/iw_cxgb/iw_cxgb_iwch_mem.c#1 add .. //depot/projects/ethng/src/sys/modules/cxgb/iw_cxgb/Makefile#6 edit Differences ... ==== //depot/projects/ethng/src/sys/dev/cxgb/cxgb_osdep.h#16 (text+ko) ==== @@ -169,6 +169,9 @@ struct mtx mr_lock; }; +struct buf_ring *buf_ring_alloc(int count, int flags); +void buf_ring_free(struct buf_ring *); + static __inline int buf_ring_count(struct buf_ring *mr) { ==== //depot/projects/ethng/src/sys/dev/cxgb/sys/cxgb_support.c#5 (text+ko) ==== @@ -299,3 +299,26 @@ uma_zfree(zone, vec[i]); } +struct buf_ring * +buf_ring_alloc(int count, int flags) +{ + struct buf_ring *br; + + KASSERT(powerof2(count), ("buf ring must be size power of 2")); + + br = malloc(sizeof(struct buf_ring), M_DEVBUF, flags|M_ZERO); + if (br == NULL) + return (NULL); + + br->mr_ring = malloc(sizeof(caddr_t)*count, M_DEVBUF, flags|M_ZERO); + if (br->mr_ring == NULL) { + free(br, M_DEVBUF); + return (NULL); + } + + mtx_init(&br->mr_lock, "buf ring", NULL, MTX_DUPOK|MTX_DEF); + br->br_size = count; + br->br_prod = br->br_cons = 0; + + return (br); +} ==== //depot/projects/ethng/src/sys/dev/cxgb/ulp/iw_cxgb/iw_cxgb_cxio_hal.h#4 (text+ko) ==== @@ -36,14 +36,14 @@ }; struct cxio_hal_resource { - struct kfifo *tpt_fifo; - spinlock_t tpt_fifo_lock; - struct kfifo *qpid_fifo; - spinlock_t qpid_fifo_lock; - struct kfifo *cqid_fifo; - spinlock_t cqid_fifo_lock; - struct kfifo *pdid_fifo; - spinlock_t pdid_fifo_lock; + struct buf_ring *tpt_fifo; + struct mtx tpt_fifo_lock; + struct buf_ring *qpid_fifo; + struct mtx qpid_fifo_lock; + struct buf_ring *cqid_fifo; + struct mtx cqid_fifo_lock; + struct buf_ring *pdid_fifo; + struct mtx pdid_fifo_lock; }; struct cxio_qpid { @@ -214,4 +214,64 @@ #define PAGE_ALIGN(x) roundup2((x), PAGE_SIZE) +#include <sys/blist.h> +struct gen_pool { + blist_t gen_list; + daddr_t gen_base; + int gen_chunk_shift; +}; + +static __inline struct gen_pool * +gen_pool_create(daddr_t base, u_int chunk_shift, u_int len) +{ + struct gen_pool *gp; + + gp = malloc(sizeof(struct gen_pool), M_DEVBUF, M_NOWAIT); + if (gp == NULL) + return (NULL); + + gp->gen_list = blist_create(len >> chunk_shift); + if (gp->gen_list == NULL) { + free(gp, M_DEVBUF); + return (NULL); + } + gp->gen_base = base; + gp->gen_chunk_shift = chunk_shift; + + return (gp); +} + +static __inline unsigned long +gen_pool_alloc(struct gen_pool *gp, int size) +{ + int chunks; + daddr_t blkno; + + chunks = size >> gp->gen_chunk_shift; + blkno = blist_alloc(gp->gen_list, chunks); + + if (blkno == SWAPBLK_NONE) + return (0); + + return (gp->gen_base + blkno); +} + +static __inline void +gen_pool_free(struct gen_pool *gp, daddr_t address, int size) +{ + int chunks; + daddr_t blkno; + + chunks = size >> gp->gen_chunk_shift; + blkno = address - gp->gen_base; + blist_free(gp->gen_list, blkno, chunks); +} + +static __inline void +gen_pool_destroy(struct gen_pool *gp) +{ + blist_destroy(gp->gen_list); + free(gp, M_DEVBUF); +} + #endif ==== //depot/projects/ethng/src/sys/modules/cxgb/iw_cxgb/Makefile#6 (text+ko) ==== @@ -5,7 +5,8 @@ KMOD= iw_cxgb SRCS= iw_cxgb_iwch.c iw_cxgb_iwch_cm.c iw_cxgb_cxio_hal.c -SRCS+= iw_cxgb_iwch_provider.c iw_cxgb_iwch_qp.c +SRCS+= iw_cxgb_iwch_provider.c iw_cxgb_iwch_qp.c iw_cxgb_cxio_resource.c +SRCS+= iw_cxgb_iwch_ev.c iw_cxgb_iwch_mem.c iw_cxgb_cxio_dbg.c iw_cxgb_iwch_cq.c SRCS+= bus_if.h device_if.h opt_sched.h pci_if.h pcib_if.h CFLAGS+= -DCONFIG_CHELSIO_T3_CORE -g -DCONFIG_DEFINED -I${CXGB} -DSMP
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