From owner-svn-src-all@freebsd.org Fri Jan 12 14:52:05 2018 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 3DAF3E69213; Fri, 12 Jan 2018 14:52:05 +0000 (UTC) (envelope-from andrew@freebsd.org) Received: from fry.fubar.geek.nz (fry.fubar.geek.nz [139.59.165.16]) by mx1.freebsd.org (Postfix) with ESMTP id CE4FE6E1F0; Fri, 12 Jan 2018 14:52:04 +0000 (UTC) (envelope-from andrew@freebsd.org) Received: from [IPv6:2001:630:212:2a8:ad58:428a:6221:67a0] (unknown [IPv6:2001:630:212:2a8:ad58:428a:6221:67a0]) by fry.fubar.geek.nz (Postfix) with ESMTPSA id 9C19C4E78C; Fri, 12 Jan 2018 14:52:03 +0000 (UTC) From: Andrew Turner Message-Id: Mime-Version: 1.0 (Mac OS X Mail 11.2 \(3445.5.20\)) Subject: Re: svn commit: r327876 - in head/sys/arm64: arm64 include Date: Fri, 12 Jan 2018 14:52:02 +0000 In-Reply-To: Cc: Marcin Wojtas , src-committers , svn-src-all@freebsd.org, svn-src-head@freebsd.org To: Warner Losh References: <201801121401.w0CE1cW4058239@repo.freebsd.org> X-Mailer: Apple Mail (2.3445.5.20) Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.25 X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Jan 2018 14:52:05 -0000 > On 12 Jan 2018, at 14:37, Warner Losh wrote: >=20 >=20 >=20 > On Fri, Jan 12, 2018 at 7:15 AM, Andrew Turner > wrote: >=20 >=20 >> On 12 Jan 2018, at 14:10, Marcin Wojtas > wrote: >>=20 >> Hi Andrew, >>=20 >>=20 >>=20 >> 2018-01-12 15:01 GMT+01:00 Andrew Turner >: >>> Author: andrew >>> Date: Fri Jan 12 14:01:38 2018 >>> New Revision: 327876 >>> URL: https://svnweb.freebsd.org/changeset/base/327876 = >>>=20 >>> Log: >>> Workaround Spectre Variant 2 on arm64. >>>=20 >>> We need to handle two cases: >>>=20 >>> 1. One process attacking another process. >>> 2. A process attacking the kernel. >>>=20 >>> For the first case we clear the branch predictor state on context = switch >>> between different processes. For the second we do this when taking = an >>> instruction abort on a non-userspace address. >>>=20 >>> To clear the branch predictor state a per-CPU function pointer has = been >>> added. This is set by the new cpu errata code based on if the CPU = is >>> known to be affected. >>>=20 >>> On Cortex-A57, A72, A73, and A75 we call into the PSCI firmware as = newer >>> versions of this will clear the branch predictor state for us. >>>=20 >>> It has been reported the ThunderX is unaffected, however the = ThunderX2 is >>> vulnerable. The Qualcomm Falkor core is also affected. As FreeBSD = doesn't >>> yet run on the ThunderX2 or Falkor no workaround is included for = these CPUs. >>=20 >> Regardless ThunderX2 / Falkor work-arounds, do I understand correctly >> that pure CA72 machines, such as Marvell Armada 7k/8k are immune to >> Variant 2 now? >=20 > It is my understanding that the A72 will be immune with this patch and = an updated Arm Trusted Firmware as documented in [1]. >=20 > Andrew >=20 > [1] = https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firm= ware-Security-Advisory-TFV-6 = >=20 > Are you also working on aarch32 mitigation? No. I think a similar technique could be used, however as aarch32 has = instructions to invalidate the branch predictor these can be used = directly. Andrew=