From owner-svn-src-projects@FreeBSD.ORG Wed Jan 21 06:17:01 2009 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 97E72106566B; Wed, 21 Jan 2009 06:17:01 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 85B9E8FC17; Wed, 21 Jan 2009 06:17:01 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n0L6H11G068412; Wed, 21 Jan 2009 06:17:01 GMT (envelope-from gonzo@svn.freebsd.org) Received: (from gonzo@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n0L6H1Tr068411; Wed, 21 Jan 2009 06:17:01 GMT (envelope-from gonzo@svn.freebsd.org) Message-Id: <200901210617.n0L6H1Tr068411@svn.freebsd.org> From: Oleksandr Tymoshenko Date: Wed, 21 Jan 2009 06:17:01 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r187515 - projects/mips/sys/mips/atheros X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Jan 2009 06:17:02 -0000 Author: gonzo Date: Wed Jan 21 06:17:01 2009 New Revision: 187515 URL: http://svn.freebsd.org/changeset/base/187515 Log: - Change register/bitnumber/masks naming convention (again) o For register names use AR71XX_REGISTER_NAME (prefix varies depending on platform AR71XX/AR91XX/... Yes, let's hope other families are on their way to tree, they call it positive thinking) o For bit number use REGISTER_NAME_FIELD_NAME o For field mask use REGISTER_NAME_FIELD_NAME_MASK Modified: projects/mips/sys/mips/atheros/ar71xxreg.h Modified: projects/mips/sys/mips/atheros/ar71xxreg.h ============================================================================== --- projects/mips/sys/mips/atheros/ar71xxreg.h Wed Jan 21 05:54:00 2009 (r187514) +++ projects/mips/sys/mips/atheros/ar71xxreg.h Wed Jan 21 06:17:01 2009 (r187515) @@ -32,25 +32,24 @@ #define ATH_WRITE_REG(reg, val) \ *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val) -#define ATH_UART_ADDR 0x18020000 +#define AR71XX_UART_ADDR 0x18020000 /* APB registers */ /* * APB interrupt status and mask register and interrupt bit numbers for */ -#define ATH_MISC_INTR_STATUS 0x18060010 -#define ATH_MISC_INTR_MASK 0x18060014 -#define ATH_INT_MISC_TIMER 0 -#define ATH_INT_MISC_ERROR 1 -#define ATH_INT_MISC_GPIO 2 -#define ATH_INT_MISC_UART 3 -#define ATH_INT_MISC_WATCHDOG 4 -#define ATH_INT_MISC_PERF 5 -#define ATH_INT_MISC_OHCI 6 -#define ATH_INT_MISC_DMA 7 +#define AR71XX_MISC_INTR_STATUS 0x18060010 +#define AR71XX_MISC_INTR_MASK 0x18060014 +#define MISC_INTR_TIMER 0 +#define MISC_INTR_ERROR 1 +#define MISC_INTR_GPIO 2 +#define MISC_INTR_UART 3 +#define MISC_INTR_WATCHDOG 4 +#define MISC_INTR_PERF 5 +#define MISC_INTR_OHCI 6 +#define MISC_INTR_DMA 7 - -#define ATH_RST_RESET 0x18060024 +#define AR71XX_RST_RESET 0x18060024 #define RST_RESET_CPU_COLD_RESET (1 << 20) /* Cold reset */ #define RST_RESET_FULL_CHIP_RESET (1 << 24) /* Same as pulling the reset pin */