From owner-freebsd-hackers Wed Sep 6 10:00:55 1995 Return-Path: hackers-owner Received: (from majordom@localhost) by freefall.freebsd.org (8.6.11/8.6.6) id KAA21735 for hackers-outgoing; Wed, 6 Sep 1995 10:00:55 -0700 Received: from localhost.lightside.com (user52.lightside.com [198.81.209.52]) by freefall.freebsd.org (8.6.11/8.6.6) with ESMTP id KAA21729 for ; Wed, 6 Sep 1995 10:00:53 -0700 Received: (from jehamby@localhost) by localhost.lightside.com (8.6.11/8.6.9) id JAA00180; Wed, 6 Sep 1995 09:59:54 -0700 Date: Wed, 6 Sep 1995 09:59:53 -0700 (PDT) From: Jake Hamby X-Sender: jehamby@localhost To: Marty Leisner cc: Mats Lofkvist , hackers@freebsd.org Subject: Re: AMD dx4-100 - Any good? In-Reply-To: <9509061458.AA21913@gnu.mc.xerox.com> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: hackers-owner@freebsd.org Precedence: bulk On Wed, 6 Sep 1995, Marty Leisner wrote: > while we're on the topic of cache, > > Are there are good performance studies of the effect of > L2 cache on 486/DX4100 /DX2-66/DX2-50 > > I've never been exposed to a good discussion of cache...one > system I have has what looks like a socket for cache (i.e. something > like simms shaped differently), another system uses actual chips... > > I have some sram chips, and had a bear of a time plugging them in... > (I didn't)... > > Should I insert the chips into carriers? About a decade ago, when > I was doing hardware, it made life much, much easier... > Most 486/Pentium systems these days seem to come with 256k of L2 cache. If not, you can add it for under $50 if you know what chips to buy (the motherboard vendor or retailer should be able to help you here). When you boot up, most BIOS's will tell you how much cache is installed on the power-on screen. As for performance improvement, it should be quite dramatic, but individual motherboards vary as to effectiveness. I do remember a Windows 3.1 program called Wintune (you can download from http://www.winmag.com/) which repeatedly accesses memory in larger and larger arrays and displays a graph of speed which should drop off when the array gets too big to fit in the L2 cache. ------------------------------------------------------------------------------- Jake Hamby | E-Mail: jehamby@lightside.com Student, Cal Poly University, Pomona | System Administrator, JPL -------------------------------------------------------------------------------