From owner-svn-src-all@FreeBSD.ORG Fri May 4 02:26:16 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 2494E106564A; Fri, 4 May 2012 02:26:16 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 0FE718FC08; Fri, 4 May 2012 02:26:16 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q442QF8X081454; Fri, 4 May 2012 02:26:15 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q442QFfp081451; Fri, 4 May 2012 02:26:15 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201205040226.q442QFfp081451@svn.freebsd.org> From: Adrian Chadd Date: Fri, 4 May 2012 02:26:15 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r234992 - head/sys/mips/atheros X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 May 2012 02:26:16 -0000 Author: adrian Date: Fri May 4 02:26:15 2012 New Revision: 234992 URL: http://svn.freebsd.org/changeset/base/234992 Log: Disable setting the MII port speed. This seems to break at least my test board here (AR71xx + AR8316 switch PHY). Since I do have a whole sleuth of "normal" PHY boards (with an AR71xx on a normal PHY port), I'll do some further testing with those to determine whether this is a general issue, or whether it's limited to the behaviour of the "fake" dedicated PHY port mode on these atheros switches. Modified: head/sys/mips/atheros/if_arge.c Modified: head/sys/mips/atheros/if_arge.c ============================================================================== --- head/sys/mips/atheros/if_arge.c Fri May 4 01:35:13 2012 (r234991) +++ head/sys/mips/atheros/if_arge.c Fri May 4 02:26:15 2012 (r234992) @@ -932,7 +932,19 @@ arge_set_pll(struct arge_softc *sc, int ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed, pll); /* set MII registers */ + /* + * This was introduced to match what the Linux ag71xx ethernet + * driver does. For the AR71xx case, it does set the port + * MII speed. However, if this is done, non-gigabit speeds + * are not at all reliable when speaking via RGMII through + * 'bridge' PHY port that's pretending to be a local PHY. + * + * Until that gets root caused, and until an AR71xx + normal + * PHY board is tested, leave this disabled. + */ +#if 0 ar71xx_device_set_mii_speed(sc->arge_mac_unit, if_speed); +#endif }