From owner-freebsd-amd64@FreeBSD.ORG Wed Apr 6 16:00:06 2005 Return-Path: Delivered-To: freebsd-amd64@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 7566616A4CE for ; Wed, 6 Apr 2005 16:00:06 +0000 (GMT) Received: from mailgate2.zdv.Uni-Mainz.DE (mailgate2.zdv.Uni-Mainz.DE [134.93.178.130]) by mx1.FreeBSD.org (Postfix) with ESMTP id 2A07143D45 for ; Wed, 6 Apr 2005 16:00:06 +0000 (GMT) (envelope-from ohartman@mail.uni-mainz.de) Received: from [213.6.72.97] (A4861.a.pppool.de [213.6.72.97]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mailgate2.zdv.Uni-Mainz.DE (Postfix) with ESMTP id 6B1B130006F7 for ; Wed, 6 Apr 2005 18:00:04 +0200 (CEST) Message-ID: <42540781.7000608@mail.uni-mainz.de> Date: Wed, 06 Apr 2005 18:00:01 +0200 From: "O. Hartmann" Organization: Institut =?ISO-8859-15?Q?f=FCr_Geophysik?= User-Agent: Mozilla/5.0 (X11; U; FreeBSD amd64; de-AT; rv:1.7.6) Gecko/20050328 X-Accept-Language: de-de, en MIME-Version: 1.0 To: amd64@freebsd.org Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Virus-Scanned: by amavisd-new at uni-mainz.de Subject: Some questions about Winchester/Newcastle cores of Athlon64 X-BeenThere: freebsd-amd64@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Porting FreeBSD to the AMD64 platform List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Apr 2005 16:00:06 -0000 Dear Sirs. In some discussions I read about some memory controler issues of Winchester based Athlon64 cores. The CPU will downgrade to DDR333 if 4 double sided memory modules are present in a system. I also read about a rumor nVidias nForce4 chipset is capable to handle 4 double sided memory modules with a Winchester based CPU core, but throttling down 1T to 2T access cycles, but remeains in DDR400 mode. Is this also an issue of the Newcastle based CPU cores or is this a bug in the Winchester cores? The oncoming Venice/San Diego cores of Athlon64 CPUs are said to be fixed and capable of driving 4 double sided memory modules. Is this weird memory controlling behaviour also an issue on Opteron CPUs? These questions may sound stupid, but I think many of the developers here and hardware thugs did a lot of stuff and thaughts about this and maybe someone is willing to answer me. Thanks a lot in advance, Oliver