From owner-svn-src-head@FreeBSD.ORG Sat Apr 11 17:16:33 2015 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 3CA3F155; Sat, 11 Apr 2015 17:16:33 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 23849D29; Sat, 11 Apr 2015 17:16:33 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t3BHGWq6024019; Sat, 11 Apr 2015 17:16:32 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t3BHGOtr023984; Sat, 11 Apr 2015 17:16:24 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201504111716.t3BHGOtr023984@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Sat, 11 Apr 2015 17:16:24 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r281438 - in head/sys: arm/amlogic/aml8726 arm/freescale/vybrid arm/samsung/exynos arm/samsung/s3c2xx0 dev/uart mips/adm5120 mips/atheros mips/cavium mips/rt305x sparc64/pci X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 11 Apr 2015 17:16:33 -0000 Author: andrew Date: Sat Apr 11 17:16:23 2015 New Revision: 281438 URL: https://svnweb.freebsd.org/changeset/base/281438 Log: Add support for the uart classes to set their default register shift value. This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week Modified: head/sys/arm/amlogic/aml8726/uart_dev_aml8726.c head/sys/arm/freescale/vybrid/vf_uart.c head/sys/arm/samsung/exynos/exynos_uart.c head/sys/arm/samsung/s3c2xx0/uart_dev_s3c2410.c head/sys/dev/uart/uart_bus.h head/sys/dev/uart/uart_bus_fdt.c head/sys/dev/uart/uart_core.c head/sys/dev/uart/uart_cpu.h head/sys/dev/uart/uart_cpu_fdt.c head/sys/dev/uart/uart_dev_imx.c head/sys/dev/uart/uart_dev_lpc.c head/sys/dev/uart/uart_dev_msm.c head/sys/dev/uart/uart_dev_ns8250.c head/sys/dev/uart/uart_dev_pl011.c head/sys/dev/uart/uart_dev_quicc.c head/sys/dev/uart/uart_dev_sab82532.c head/sys/dev/uart/uart_dev_ti8250.c head/sys/dev/uart/uart_dev_z8530.c head/sys/mips/adm5120/uart_dev_adm5120.c head/sys/mips/atheros/uart_dev_ar933x.c head/sys/mips/cavium/uart_dev_oct16550.c head/sys/mips/rt305x/uart_dev_rt305x.c head/sys/sparc64/pci/sbbc.c Modified: head/sys/arm/amlogic/aml8726/uart_dev_aml8726.c ============================================================================== --- head/sys/arm/amlogic/aml8726/uart_dev_aml8726.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/arm/amlogic/aml8726/uart_dev_aml8726.c Sat Apr 11 17:16:23 2015 (r281438) @@ -724,7 +724,8 @@ struct uart_class uart_aml8726_class = { sizeof(struct uart_softc), .uc_ops = &aml8726_uart_ops, .uc_range = 24, - .uc_rclk = 0 + .uc_rclk = 0, + .uc_rshift = 0 }; static struct ofw_compat_data compat_data[] = { Modified: head/sys/arm/freescale/vybrid/vf_uart.c ============================================================================== --- head/sys/arm/freescale/vybrid/vf_uart.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/arm/freescale/vybrid/vf_uart.c Sat Apr 11 17:16:23 2015 (r281438) @@ -276,7 +276,8 @@ static struct uart_class uart_vybrid_cla sizeof(struct vf_uart_softc), .uc_ops = &uart_vybrid_ops, .uc_range = 0x100, - .uc_rclk = 24000000 /* TODO: get value from CCM */ + .uc_rclk = 24000000, /* TODO: get value from CCM */ + .uc_rshift = 0 }; static struct ofw_compat_data compat_data[] = { Modified: head/sys/arm/samsung/exynos/exynos_uart.c ============================================================================== --- head/sys/arm/samsung/exynos/exynos_uart.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/arm/samsung/exynos/exynos_uart.c Sat Apr 11 17:16:23 2015 (r281438) @@ -380,6 +380,7 @@ static struct uart_class uart_exynos4210 .uc_ops = &uart_exynos4210_ops, .uc_range = 8, .uc_rclk = 0, + .uc_rshift = 0 }; static struct ofw_compat_data compat_data[] = { Modified: head/sys/arm/samsung/s3c2xx0/uart_dev_s3c2410.c ============================================================================== --- head/sys/arm/samsung/s3c2xx0/uart_dev_s3c2410.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/arm/samsung/s3c2xx0/uart_dev_s3c2410.c Sat Apr 11 17:16:23 2015 (r281438) @@ -402,4 +402,5 @@ struct uart_class uart_s3c2410_class = { .uc_ops = &uart_s3c2410_ops, .uc_range = 8, .uc_rclk = 0, + .uc_rshift = 0 }; Modified: head/sys/dev/uart/uart_bus.h ============================================================================== --- head/sys/dev/uart/uart_bus.h Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_bus.h Sat Apr 11 17:16:23 2015 (r281438) @@ -70,6 +70,7 @@ struct uart_class { struct uart_ops *uc_ops; /* Low-level console operations. */ u_int uc_range; /* Bus space address range. */ u_int uc_rclk; /* Default rclk for this device. */ + u_int uc_rshift; /* Default regshift for this device. */ }; struct uart_softc { Modified: head/sys/dev/uart/uart_bus_fdt.c ============================================================================== --- head/sys/dev/uart/uart_bus_fdt.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_bus_fdt.c Sat Apr 11 17:16:23 2015 (r281438) @@ -83,16 +83,10 @@ uart_fdt_get_clock(phandle_t node, pcell int uart_fdt_get_shift(phandle_t node, pcell_t *cell) { -#ifdef __aarch64__ -#define DEFAULT_SHIFT 2 -#else -#define DEFAULT_SHIFT 0 -#endif if ((OF_getencprop(node, "reg-shift", cell, sizeof(*cell))) <= 0) - *cell = DEFAULT_SHIFT; + return (-1); return (0); -#undef DEFAULT_SHIFT } static uintptr_t @@ -130,7 +124,8 @@ uart_fdt_probe(device_t dev) if ((err = uart_fdt_get_clock(node, &clock)) != 0) return (err); - uart_fdt_get_shift(node, &shift); + if (uart_fdt_get_shift(node, &shift) != 0) + shift = uart_getregshift(sc->sc_class); return (uart_bus_probe(dev, (int)shift, (int)clock, 0, 0)); } Modified: head/sys/dev/uart/uart_core.c ============================================================================== --- head/sys/dev/uart/uart_core.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_core.c Sat Apr 11 17:16:23 2015 (r281438) @@ -88,6 +88,12 @@ uart_getrange(struct uart_class *uc) return ((uc != NULL) ? uc->uc_range : 0); } +u_int +uart_getregshift(struct uart_class *uc) +{ + return ((uc != NULL) ? uc->uc_rshift : 0); +} + /* * Schedule a soft interrupt. We do this on the 0 to !0 transition * of the TTY pending interrupt status. Modified: head/sys/dev/uart/uart_cpu.h ============================================================================== --- head/sys/dev/uart/uart_cpu.h Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_cpu.h Sat Apr 11 17:16:23 2015 (r281438) @@ -79,6 +79,7 @@ int uart_getenv(int, struct uart_devinfo const char *uart_getname(struct uart_class *); struct uart_ops *uart_getops(struct uart_class *); int uart_getrange(struct uart_class *); +u_int uart_getregshift(struct uart_class *); void uart_add_sysdev(struct uart_devinfo *); Modified: head/sys/dev/uart/uart_cpu_fdt.c ============================================================================== --- head/sys/dev/uart/uart_cpu_fdt.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_cpu_fdt.c Sat Apr 11 17:16:23 2015 (r281438) @@ -165,15 +165,6 @@ uart_cpu_getdev(int devtype, struct uart return (ENXIO); /* - * Retrieve serial attributes. - */ - uart_fdt_get_shift(node, &shift); - if (OF_getprop(node, "current-speed", &br, sizeof(br)) <= 0) - br = 0; - else - br = fdt32_to_cpu(br); - - /* * Check old style of UART definition first. Unfortunately, the common * FDT processing is not possible if we have clock, power domains and * pinmux stuff. @@ -192,6 +183,17 @@ uart_cpu_getdev(int devtype, struct uart } /* + * Retrieve serial attributes. + */ + if (uart_fdt_get_shift(node, &shift) != 0) + shift = uart_getregshift(class); + + if (OF_getprop(node, "current-speed", &br, sizeof(br)) <= 0) + br = 0; + else + br = fdt32_to_cpu(br); + + /* * Finalize configuration. */ di->bas.chan = 0; Modified: head/sys/dev/uart/uart_dev_imx.c ============================================================================== --- head/sys/dev/uart/uart_dev_imx.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_dev_imx.c Sat Apr 11 17:16:23 2015 (r281438) @@ -298,7 +298,8 @@ static struct uart_class uart_imx_class sizeof(struct imx_uart_softc), .uc_ops = &uart_imx_uart_ops, .uc_range = 0x100, - .uc_rclk = 24000000 /* TODO: get value from CCM */ + .uc_rclk = 24000000, /* TODO: get value from CCM */ + .uc_rshift = 0 }; static struct ofw_compat_data compat_data[] = { Modified: head/sys/dev/uart/uart_dev_lpc.c ============================================================================== --- head/sys/dev/uart/uart_dev_lpc.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_dev_lpc.c Sat Apr 11 17:16:23 2015 (r281438) @@ -428,7 +428,8 @@ static struct uart_class uart_lpc_class sizeof(struct lpc_ns8250_softc), .uc_ops = &uart_lpc_ns8250_ops, .uc_range = 8, - .uc_rclk = DEFAULT_RCLK + .uc_rclk = DEFAULT_RCLK, + .uc_rshift = 0 }; static struct ofw_compat_data compat_data[] = { Modified: head/sys/dev/uart/uart_dev_msm.c ============================================================================== --- head/sys/dev/uart/uart_dev_msm.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_dev_msm.c Sat Apr 11 17:16:23 2015 (r281438) @@ -566,6 +566,7 @@ static struct uart_class uart_msm_class .uc_ops = &uart_msm_ops, .uc_range = 8, .uc_rclk = DEF_CLK, + .uc_rshift = 0 }; static struct ofw_compat_data compat_data[] = { Modified: head/sys/dev/uart/uart_dev_ns8250.c ============================================================================== --- head/sys/dev/uart/uart_dev_ns8250.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_dev_ns8250.c Sat Apr 11 17:16:23 2015 (r281438) @@ -378,7 +378,8 @@ struct uart_class uart_ns8250_class = { sizeof(struct ns8250_softc), .uc_ops = &uart_ns8250_ops, .uc_range = 8, - .uc_rclk = DEFAULT_RCLK + .uc_rclk = DEFAULT_RCLK, + .uc_rshift = 0 }; #ifdef FDT Modified: head/sys/dev/uart/uart_dev_pl011.c ============================================================================== --- head/sys/dev/uart/uart_dev_pl011.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_dev_pl011.c Sat Apr 11 17:16:23 2015 (r281438) @@ -273,7 +273,8 @@ static struct uart_class uart_pl011_clas sizeof(struct uart_pl011_softc), .uc_ops = &uart_pl011_ops, .uc_range = 0x48, - .uc_rclk = 0 + .uc_rclk = 0, + .uc_rshift = 2 }; static struct ofw_compat_data compat_data[] = { Modified: head/sys/dev/uart/uart_dev_quicc.c ============================================================================== --- head/sys/dev/uart/uart_dev_quicc.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_dev_quicc.c Sat Apr 11 17:16:23 2015 (r281438) @@ -271,7 +271,8 @@ struct uart_class uart_quicc_class = { sizeof(struct quicc_softc), .uc_ops = &uart_quicc_ops, .uc_range = 2, - .uc_rclk = DEFAULT_RCLK + .uc_rclk = DEFAULT_RCLK, + .uc_rshift = 0 }; #define SIGCHG(c, i, s, d) \ Modified: head/sys/dev/uart/uart_dev_sab82532.c ============================================================================== --- head/sys/dev/uart/uart_dev_sab82532.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_dev_sab82532.c Sat Apr 11 17:16:23 2015 (r281438) @@ -391,7 +391,8 @@ struct uart_class uart_sab82532_class = sizeof(struct sab82532_softc), .uc_ops = &uart_sab82532_ops, .uc_range = 64, - .uc_rclk = DEFAULT_RCLK + .uc_rclk = DEFAULT_RCLK, + .uc_rshift = 0 }; #define SIGCHG(c, i, s, d) \ Modified: head/sys/dev/uart/uart_dev_ti8250.c ============================================================================== --- head/sys/dev/uart/uart_dev_ti8250.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_dev_ti8250.c Sat Apr 11 17:16:23 2015 (r281438) @@ -137,7 +137,8 @@ static struct uart_class uart_ti8250_cla sizeof(struct ti8250_softc), .uc_ops = &uart_ns8250_ops, .uc_range = 0x88, - .uc_rclk = 48000000 + .uc_rclk = 48000000, + .uc_rshift = 0 }; static struct ofw_compat_data compat_data[] = { {"ti,ns16550", (uintptr_t)&uart_ti8250_class}, Modified: head/sys/dev/uart/uart_dev_z8530.c ============================================================================== --- head/sys/dev/uart/uart_dev_z8530.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/dev/uart/uart_dev_z8530.c Sat Apr 11 17:16:23 2015 (r281438) @@ -307,7 +307,8 @@ struct uart_class uart_z8530_class = { sizeof(struct z8530_softc), .uc_ops = &uart_z8530_ops, .uc_range = 2, - .uc_rclk = DEFAULT_RCLK + .uc_rclk = DEFAULT_RCLK, + .uc_rshift = 0 }; #define SIGCHG(c, i, s, d) \ Modified: head/sys/mips/adm5120/uart_dev_adm5120.c ============================================================================== --- head/sys/mips/adm5120/uart_dev_adm5120.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/mips/adm5120/uart_dev_adm5120.c Sat Apr 11 17:16:23 2015 (r281438) @@ -175,7 +175,8 @@ struct uart_class uart_adm5120_uart_clas sizeof(struct adm5120_uart_softc), .uc_ops = &uart_adm5120_uart_ops, .uc_range = 1, /* use hinted range */ - .uc_rclk = 62500000 + .uc_rclk = 62500000, + .uc_rshift = 0 }; #define SIGCHG(c, i, s, d) \ Modified: head/sys/mips/atheros/uart_dev_ar933x.c ============================================================================== --- head/sys/mips/atheros/uart_dev_ar933x.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/mips/atheros/uart_dev_ar933x.c Sat Apr 11 17:16:23 2015 (r281438) @@ -351,7 +351,8 @@ struct uart_class uart_ar933x_class = { sizeof(struct ar933x_softc), .uc_ops = &uart_ar933x_ops, .uc_range = 8, - .uc_rclk = DEFAULT_RCLK + .uc_rclk = DEFAULT_RCLK, + .uc_rshift = 0 }; #define SIGCHG(c, i, s, d) \ Modified: head/sys/mips/cavium/uart_dev_oct16550.c ============================================================================== --- head/sys/mips/cavium/uart_dev_oct16550.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/mips/cavium/uart_dev_oct16550.c Sat Apr 11 17:16:23 2015 (r281438) @@ -424,7 +424,8 @@ struct uart_class uart_oct16550_class = sizeof(struct oct16550_softc), .uc_ops = &uart_oct16550_ops, .uc_range = 8 << 3, - .uc_rclk = 0 + .uc_rclk = 0, + .uc_rshift = 0 }; #define SIGCHG(c, i, s, d) \ Modified: head/sys/mips/rt305x/uart_dev_rt305x.c ============================================================================== --- head/sys/mips/rt305x/uart_dev_rt305x.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/mips/rt305x/uart_dev_rt305x.c Sat Apr 11 17:16:23 2015 (r281438) @@ -217,7 +217,8 @@ struct uart_class uart_rt305x_uart_class sizeof(struct rt305x_uart_softc), .uc_ops = &uart_rt305x_uart_ops, .uc_range = 1, /* use hinted range */ - .uc_rclk = SYSTEM_CLOCK + .uc_rclk = SYSTEM_CLOCK, + .uc_rshift = 0 }; #define SIGCHG(c, i, s, d) \ Modified: head/sys/sparc64/pci/sbbc.c ============================================================================== --- head/sys/sparc64/pci/sbbc.c Sat Apr 11 16:00:33 2015 (r281437) +++ head/sys/sparc64/pci/sbbc.c Sat Apr 11 17:16:23 2015 (r281438) @@ -813,7 +813,8 @@ struct uart_class uart_sbbc_class = { sizeof(struct uart_softc), .uc_ops = &sbbc_uart_ops, .uc_range = 1, - .uc_rclk = 0x5bbc /* arbitrary */ + .uc_rclk = 0x5bbc, /* arbitrary */ + .uc_rshift = 0 }; #define SIGCHG(c, i, s, d) \