From owner-freebsd-net@FreeBSD.ORG Fri Jun 19 00:50:06 2009 Return-Path: Delivered-To: freebsd-net@hub.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 460FC106564A for ; Fri, 19 Jun 2009 00:50:06 +0000 (UTC) (envelope-from gnats@FreeBSD.org) Received: from freefall.freebsd.org (freefall.freebsd.org [IPv6:2001:4f8:fff6::28]) by mx1.freebsd.org (Postfix) with ESMTP id 33D708FC14 for ; Fri, 19 Jun 2009 00:50:06 +0000 (UTC) (envelope-from gnats@FreeBSD.org) Received: from freefall.freebsd.org (gnats@localhost [127.0.0.1]) by freefall.freebsd.org (8.14.3/8.14.3) with ESMTP id n5J0o6AX076485 for ; Fri, 19 Jun 2009 00:50:06 GMT (envelope-from gnats@freefall.freebsd.org) Received: (from gnats@localhost) by freefall.freebsd.org (8.14.3/8.14.3/Submit) id n5J0o6PN076484; Fri, 19 Jun 2009 00:50:06 GMT (envelope-from gnats) Date: Fri, 19 Jun 2009 00:50:06 GMT Message-Id: <200906190050.n5J0o6PN076484@freefall.freebsd.org> To: freebsd-net@FreeBSD.org From: Pyun YongHyeon Cc: Subject: Re: kern/124127: [msk] watchdog timeout (missed Tx interrupts) -- recovering X-BeenThere: freebsd-net@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list Reply-To: Pyun YongHyeon List-Id: Networking and TCP/IP with FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 Jun 2009 00:50:06 -0000 The following reply was made to PR kern/124127; it has been noted by GNATS. From: Pyun YongHyeon To: sam Cc: yongari@freebsd.org, bug-followup@FreeBSD.org Subject: Re: kern/124127: [msk] watchdog timeout (missed Tx interrupts) -- recovering Date: Fri, 19 Jun 2009 09:40:46 +0900 --pQhZXvAqiZgbeUkD Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Jul 31, 2008 at 04:06:42PM +0400, sam wrote: > ----------------------------------------------- > Jul 30 11:13:47 moon3 kernel: msk0: watchdog timeout (missed Tx > interrupts) -- recovering > Jul 30 11:14:44 moon3 kernel: msk0: watchdog timeout (missed Tx > interrupts) -- recovering > ----------------------------------------------- > > ----------------------------------------------- > Jul 29 23:18:28 moon3 kernel: mskc0: Ethernet> port 0xdf00-0xdfff mem 0xdeefc000-0xdeefffff irq 16 at device > 0.0 on pci2 > Jul 29 23:18:28 moon3 kernel: msk0: Yukon EC Id 0xb6 Rev 0x02> on mskc0 > > Jul 29 23:18:28 moon3 kernel: miibus0: on msk0 > ----------------------------------------------- > > ----------------------------------------------- > FreeBSD moon3 7.0-RELEASE-p2 FreeBSD 7.0-RELEASE-p2 #5: Wed Jul 27 > 15:00:14 MSD 2008 root@moon3:/usr/src/sys/i386/compile/MOON3 i386 > ----------------------------------------------- > > I confirm this problem. > > /Vladimir Ermakov > > Would you try attached patch and let me know hot it goes? --pQhZXvAqiZgbeUkD Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="msk.EC.patch" Index: sys/dev/msk/if_msk.c =================================================================== --- sys/dev/msk/if_msk.c (revision 194467) +++ sys/dev/msk/if_msk.c (working copy) @@ -1387,27 +1387,26 @@ CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); /* Set the status list last index. */ CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); - if (sc->msk_hw_id == CHIP_ID_YUKON_EC && - sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { - /* WA for dev. #4.3 */ - CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); - /* WA for dev. #4.18 */ - CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); - CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); - } else { - CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); - CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); - if (sc->msk_hw_id == CHIP_ID_YUKON_XL && - sc->msk_hw_rev == CHIP_REV_YU_XL_A0) - CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); - else - CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); - CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); - } /* - * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. + * XXX + * Interrupt moderation and coalescing frames should be + * controllable with sysctl variables or loader tunables + * but the relationship between status updates and + * interrupt moderation are not clear to me. Some hardware + * revisions seem to very sensitive to these parameters + * and could be resulted in poor performance as well as + * non-working situation if improper values were chosen. */ + CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); + CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); + if (sc->msk_hw_id == CHIP_ID_YUKON_XL && + sc->msk_hw_rev == CHIP_REV_YU_XL_A0) + CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); + else + CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); + CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, MSK_USECS(sc, 30)); + CSR_WRITE_4(sc, STAT_LEV_TIMER_INI, MSK_USECS(sc, 50)); /* Enable status unit. */ CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); --pQhZXvAqiZgbeUkD--