Date: Sat, 19 Nov 2016 18:03:46 +0000 (UTC) From: Ruslan Bukin <br@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r308859 - in head/sys/mips: conf mips Message-ID: <201611191803.uAJI3kJX003228@repo.freebsd.org>
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Author: br Date: Sat Nov 19 18:03:46 2016 New Revision: 308859 URL: https://svnweb.freebsd.org/changeset/base/308859 Log: Enable SMP on Ingenic JZ4780. It is required to proceed full cache flush before we can use wait instruction on multicore, so use nop instead for now. Submitted by: kan Sponsored by: DARPA, AFRL Modified: head/sys/mips/conf/JZ4780 head/sys/mips/mips/exception.S Modified: head/sys/mips/conf/JZ4780 ============================================================================== --- head/sys/mips/conf/JZ4780 Sat Nov 19 17:51:02 2016 (r308858) +++ head/sys/mips/conf/JZ4780 Sat Nov 19 18:03:46 2016 (r308859) @@ -53,7 +53,7 @@ options INVARIANT_SUPPORT #Extra sanity #options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed # Make an SMP-capable kernel by default -# options SMP # Symmetric MultiProcessor Kernel +options SMP # Symmetric MultiProcessor Kernel device loop device ether Modified: head/sys/mips/mips/exception.S ============================================================================== --- head/sys/mips/mips/exception.S Sat Nov 19 17:51:02 2016 (r308858) +++ head/sys/mips/mips/exception.S Sat Nov 19 18:03:46 2016 (r308859) @@ -590,7 +590,11 @@ GLOBAL(MipsWaitStart) # this is 16 byt mtc0 t1, MIPS_COP_0_STATUS bnez v0, MipsWaitEnd nop +#if defined(CPU_XBURST) && defined(SMP) + nop +#else wait +#endif GLOBAL(MipsWaitEnd) # MipsWaitStart + 16 jr ra PTR_ADDU sp, sp, CALLFRAME_SIZ
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