Date: Tue, 14 Apr 2020 16:00:26 +0200 From: Heitai <heitai@minix-c11.org> To: freebsd-hackers@freebsd.org Subject: try to Compile dev/drm2 with stable svn in hard under the kernel Message-ID: <20200414160026.5eb905df@Dell-Station.lan>
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Hello,
I try to compile with the stable kernel svn source code the drm2 driver
for have the correct and hightest resolution for my intel video card at
the boot time.
Sorry for the long log, I prefer paste all I have.
I hope I'm on the correct ML and if that isn't please say me how post.
I would like have same in the loader boot prompt.
Best Regard,
See after for better reading,
Heitai
--
[___]--> my trying to debug the sys/dev/iicbus/iicbus_if.m
by iicbus_if.h
[=============]
/*
* Copyright (c) 1998 Nicolas Souchu
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
distribution. *
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: stable/12/sys/dev/iicbus/iicbus_if.m 323474 2017-09-11
23:47:49Z ian $ */
#include <sys/bus.h>
#include <dev/iicbus/iic.h>
INTERFACE iicbus(void)
CODE {
struct iicbus_nosupport
{
return (ENODEV);
} ;
struct u_int,
iicbus_default_frequency(device_t bus, u_char speed)
{
return (100000);
} ;
}
/*
* Interpret interrupt
*/
struct intr {
device_t dev;
int event;
char *buf;
} ;
/*
* iicbus callback
* Request ownership of bus
* index: IIC_REQUEST_BUS or IIC_RELEASE_BUS
* data: pointer to int containing IIC_WAIT or IIC_DONTWAIT and either
IIC_INTR or IIC_NOINTR
* This function is allowed to sleep if *data contains IIC_WAIT.
*/
struct callback {
device_t dev;
int index;
caddr_t data;
} ;
/*
* Send REPEATED_START condition
*/
struct repeated_start {
device_t dev;
u_char slave;
int timeout;
} iicbus_nosupport ;
/*)
* Send START condition
*/
struct start {
device_t dev;
u_char slave;
int timeout;
} iicbus_nosupport ;
/*
* Send STOP condition
*/
struct stop {
device_t dev;
} iicbus_nosupport ;
/*
* Read from I2C bus
*/
struct read {
device_t dev;
char *buf;
int len;
int *bytes;
int last;
int delay;
} iicbus_nosupport ;
/*
* Write to the I2C bus
*/
struct write {
device_t dev;
const char *buf;
int len;
int *bytes;
int timeout;
} iicbus_nosupport ;
/*
* Reset I2C bus
*/
struct reset {
device_t dev;
u_char speed;
u_char addr;
u_char *oldaddr;
} ;
/*
* Generalized Read/Write interface
*/
struct transfer {
device_t dev;
struct iic_msg *msgs;
uint32_t nmsgs;
} ;
/*
* Return the frequency in Hz for the bus running at the given
* symbolic speed. Only the IIC_SLOW speed has meaning, it is always
* 100KHz. The UNKNOWN, FAST, and FASTEST rates all map to the
* configured bus frequency, or 100KHz when not otherwise configured.
*/
struct u_int, get_frequency {
device_t dev;
u_char speed;
} iicbus_default_frequency ;
[=============]
[___]--> The # make buildkernel ERROR
[%===========%]
make[1]: "/usr/src/Makefile.inc1" line 344: SYSTEM_COMPILER: libclang
will be built for bootstrapping a cross-compiler. make[1]:
"/usr/src/Makefile.inc1" line 349: SYSTEM_LINKER: libclang will be
built for bootstrapping a cross-linker. In file included from
/usr/src/sys/dev/drm2/drm_dp_iic_helper.c:31:
/usr/src/sys/dev/iicbus/iicbus_if.h:32:1: error: unknown type name
'INTERFACE' INTERFACE iicbus(void) ^
/usr/src/sys/dev/iicbus/iicbus_if.h:34:1: error: expected function body
after function declarator CODE { ^
/usr/src/sys/dev/iicbus/iicbus_if.h:85:6: error: redefinition of
'iicbus_nosupport' with a different type: 'struct start' vs 'struct
repeated_start' } iicbus_nosupport ;
^
/usr/src/sys/dev/iicbus/iicbus_if.h:76:6: note: previous definition is
here } iicbus_nosupport ;
^
/usr/src/sys/dev/iicbus/iicbus_if.h:92:3: error: redefinition of
'iicbus_nosupport' with a different type: 'struct stop' vs 'struct
repeated_start' } iicbus_nosupport ;
^
/usr/src/sys/dev/iicbus/iicbus_if.h:76:6: note: previous definition is
here } iicbus_nosupport ;
^
/usr/src/sys/dev/iicbus/iicbus_if.h:104:6: error: redefinition of
'iicbus_nosupport' with a different type: 'struct read' vs 'struct
repeated_start' } iicbus_nosupport ;
^
/usr/src/sys/dev/iicbus/iicbus_if.h:76:6: note: previous definition is
here } iicbus_nosupport ;
^
/usr/src/sys/dev/iicbus/iicbus_if.h:115:6: error: redefinition of
'iicbus_nosupport' with a different type: 'struct write' vs 'struct
repeated_start' } iicbus_nosupport ;
^
/usr/src/sys/dev/iicbus/iicbus_if.h:76:6: note: previous definition is
here } iicbus_nosupport ;
^
/usr/src/sys/dev/iicbus/iicbus_if.h:142:13: error: expected identifier
or '(' struct u_int, get_frequency {
^
/usr/src/sys/dev/iicbus/iicbus_if.h:145:6: error: type specifier
missing, defaults to 'int' [-Werror,-Wimplicit-int]
} iicbus_default_frequency ;
^
/usr/src/sys/dev/drm2/drm_dp_iic_helper.c:268:2: error: use of
undeclared identifier 'iicbus_reset_desc' DEVMETHOD(iicbus_reset,
iic_dp_aux_reset), ^
/usr/src/sys/sys/bus.h:747:19: note: expanded from macro 'DEVMETHOD'
#define DEVMETHOD KOBJMETHOD
^
/usr/src/sys/sys/kobj.h:100:5: note: expanded from macro 'KOBJMETHOD'
{ &NAME##_desc, (kobjop_t) (1 ? FUNC : (NAME##_t *)NULL) }
^
<scratch space>:150:1: note: expanded from here
iicbus_reset_desc
^
/usr/src/sys/dev/drm2/drm_dp_iic_helper.c:268:2: error: expected
expression /usr/src/sys/sys/bus.h:747:19: note: expanded from macro
'DEVMETHOD' #define DEVMETHOD KOBJMETHOD
^
/usr/src/sys/sys/kobj.h:100:52: note: expanded from macro 'KOBJMETHOD'
{ &NAME##_desc, (kobjop_t) (1 ? FUNC : (NAME##_t *)NULL) }
^
/usr/src/sys/dev/drm2/drm_dp_iic_helper.c:268:2: error: use of
undeclared identifier 'iicbus_reset_t' /usr/src/sys/sys/bus.h:747:19:
note: expanded from macro 'DEVMETHOD' #define DEVMETHOD KOBJMETHOD
^
/usr/src/sys/sys/kobj.h:100:42: note: expanded from macro 'KOBJMETHOD'
{ &NAME##_desc, (kobjop_t) (1 ? FUNC : (NAME##_t *)NULL) }
^
<scratch space>:151:1: note: expanded from here
iicbus_reset_t
^
/usr/src/sys/dev/drm2/drm_dp_iic_helper.c:269:2: error: use of
undeclared identifier 'iicbus_transfer_desc' DEVMETHOD(iicbus_transfer,
iic_dp_aux_xfer), ^
/usr/src/sys/sys/bus.h:747:19: note: expanded from macro 'DEVMETHOD'
#define DEVMETHOD KOBJMETHOD
^
/usr/src/sys/sys/kobj.h:100:5: note: expanded from macro 'KOBJMETHOD'
{ &NAME##_desc, (kobjop_t) (1 ? FUNC : (NAME##_t *)NULL) }
^
<scratch space>:152:1: note: expanded from here
iicbus_transfer_desc
^
/usr/src/sys/dev/drm2/drm_dp_iic_helper.c:269:2: error: expected
expression /usr/src/sys/sys/bus.h:747:19: note: expanded from macro
'DEVMETHOD' #define DEVMETHOD KOBJMETHOD
^
/usr/src/sys/sys/kobj.h:100:52: note: expanded from macro 'KOBJMETHOD'
{ &NAME##_desc, (kobjop_t) (1 ? FUNC : (NAME##_t *)NULL) }
^
/usr/src/sys/dev/drm2/drm_dp_iic_helper.c:269:2: error: use of
undeclared identifier 'iicbus_transfer_t'; did you mean
'iicbus_transfer'? /usr/src/sys/sys/bus.h:747:19: note: expanded from
macro 'DEVMETHOD' #define DEVMETHOD KOBJMETHOD
^
/usr/src/sys/sys/kobj.h:100:42: note: expanded from macro 'KOBJMETHOD'
{ &NAME##_desc, (kobjop_t) (1 ? FUNC : (NAME##_t *)NULL) }
^
<scratch space>:153:1: note: expanded from here
iicbus_transfer_t
^
/usr/src/sys/dev/iicbus/iiconf.h:155:5: note: 'iicbus_transfer'
declared here int iicbus_transfer(device_t bus, struct iic_msg *msgs,
uint32_t nmsgs); ^
14 errors generated.
[%===========%]
<[-------------]>
# pciconf -lvc
hostb0@pci0:0:0:0: class=0x060000 card=0x024d1028
chip=0x2a408086 rev=0x07 hdr=0x00 vendor = 'Intel Corporation'
device = 'Mobile 4 Series Chipset Memory Controller Hub'
class = bridge
subclass = HOST-PCI
cap 09[e0] = vendor (length 10) Intel cap 1 version 1
vgapci0@pci0:0:2:0: class=0x030000 card=0x024d1028
chip=0x2a428086 rev=0x07 hdr=0x00 vendor = 'Intel Corporation'
device = 'Mobile 4 Series Chipset Integrated Graphics
Controller' class = display
subclass = VGA
cap 05[90] = MSI supports 1 message enabled with 1 message
cap 01[d0] = powerspec 3 supports D0 D3 current D0
vgapci1@pci0:0:2:1: class=0x038000 card=0x024d1028
chip=0x2a438086 rev=0x07 hdr=0x00 vendor = 'Intel Corporation'
device = 'Mobile 4 Series Chipset Integrated Graphics
Controller' class = display
cap 01[d0] = powerspec 3 supports D0 D3 current D0
none0@pci0:0:3:0: class=0x078000 card=0x024d1028 chip=0x2a448086
rev=0x07 hdr=0x00 vendor = 'Intel Corporation'
device = 'Mobile 4 Series Chipset MEI Controller'
class = simple comms
cap 01[50] = powerspec 3 supports D0 D3 current D0
cap 05[8c] = MSI supports 1 message, 64 bit
atapci0@pci0:0:3:2: class=0x010185 card=0x024d1028
chip=0x2a468086 rev=0x07 hdr=0x00 vendor = 'Intel Corporation'
device = 'Mobile 4 Series Chipset PT IDER Controller'
class = mass storage
subclass = ATA
cap 01[c8] = powerspec 3 supports D0 D3 current D0
cap 05[d0] = MSI supports 1 message, 64 bit
uart2@pci0:0:3:3: class=0x070002 card=0x024d1028 chip=0x2a478086
rev=0x07 hdr=0x00 vendor = 'Intel Corporation'
device = 'Mobile 4 Series Chipset AMT SOL Redirection'
class = simple comms
subclass = UART
cap 01[c8] = powerspec 3 supports D0 D3 current D0
cap 05[d0] = MSI supports 1 message, 64 bit enabled with 1 message
em0@pci0:0:25:0: class=0x020000 card=0x024d1028 chip=0x10f58086
rev=0x03 hdr=0x00 vendor = 'Intel Corporation'
device = '82567LM Gigabit Network Connection'
class = network
subclass = ethernet
cap 01[c8] = powerspec 2 supports D0 D3 current D0
cap 05[d0] = MSI supports 1 message, 64 bit enabled with 1 message
cap 13[e0] = PCI Advanced Features: FLR TP
uhci0@pci0:0:26:0: class=0x0c0300 card=0x024d1028
chip=0x29378086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation'
device = '82801I (ICH9 Family) USB UHCI Controller'
class = serial bus
subclass = USB
cap 13[50] = PCI Advanced Features: FLR TP
uhci1@pci0:0:26:1: class=0x0c0300 card=0x024d1028
chip=0x29388086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation'
device = '82801I (ICH9 Family) USB UHCI Controller'
class = serial bus
subclass = USB
cap 13[50] = PCI Advanced Features: FLR TP
uhci2@pci0:0:26:2: class=0x0c0300 card=0x024d1028
chip=0x29398086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation'
device = '82801I (ICH9 Family) USB UHCI Controller'
class = serial bus
subclass = USB
cap 13[50] = PCI Advanced Features: FLR TP
ehci0@pci0:0:26:7: class=0x0c0320 card=0x024d1028
chip=0x293c8086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation'
device = '82801I (ICH9 Family) USB2 EHCI Controller'
class = serial bus
subclass = USB
cap 01[50] = powerspec 2 supports D0 D3 current D0
cap 0a[58] = EHCI Debug Port at offset 0xa0 in map 0x14
cap 13[98] = PCI Advanced Features: FLR TP
hdac0@pci0:0:27:0: class=0x040300 card=0x024d1028
chip=0x293e8086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation'
device = '82801I (ICH9 Family) HD Audio Controller'
class = multimedia
subclass = HDA
cap 01[50] = powerspec 2 supports D0 D3 current D0
cap 05[60] = MSI supports 1 message, 64 bit enabled with 1 message
cap 10[70] = PCI-Express 1 root endpoint max data 128(128) FLR NS
ecap 0002[100] = VC 1 max VC1
ecap 0005[130] = Root Complex Link Declaration 1
pcib1@pci0:0:28:0: class=0x060400 card=0x024d1028
chip=0x29408086 rev=0x03 hdr=0x01 vendor = 'Intel Corporation'
device = '82801I (ICH9 Family) PCI Express Port 1'
class = bridge
subclass = PCI-PCI
cap 10[40] = PCI-Express 1 root port max data 128(128)
link x0(x1) speed 0.0(2.5) ASPM disabled(L0s/L1)
slot 0 power limit 65 mW HotPlug(empty) surprise
cap 05[80] = MSI supports 1 message enabled with 1 message
cap 0d[90] = PCI Bridge card=0x024d1028
cap 01[a0] = powerspec 2 supports D0 D3 current D0
ecap 0002[100] = VC 1 max VC0
ecap 0005[180] = Root Complex Link Declaration 1
pcib2@pci0:0:28:3: class=0x060400 card=0x024d1028
chip=0x29468086 rev=0x03 hdr=0x01 vendor = 'Intel Corporation'
device = '82801I (ICH9 Family) PCI Express Port 4'
class = bridge
subclass = PCI-PCI
cap 10[40] = PCI-Express 1 root port max data 128(128)
link x0(x1) speed 0.0(2.5) ASPM disabled(L0s/L1)
slot 3 power limit 65 mW HotPlug(empty) surprise
cap 05[80] = MSI supports 1 message enabled with 1 message
cap 0d[90] = PCI Bridge card=0x024d1028
cap 01[a0] = powerspec 2 supports D0 D3 current D0
ecap 0002[100] = VC 1 max VC0
ecap 0005[180] = Root Complex Link Declaration 1
uhci3@pci0:0:29:0: class=0x0c0300 card=0x024d1028
chip=0x29348086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation'
device = '82801I (ICH9 Family) USB UHCI Controller'
class = serial bus
subclass = USB
cap 13[50] = PCI Advanced Features: FLR TP
uhci4@pci0:0:29:1: class=0x0c0300 card=0x024d1028
chip=0x29358086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation'
device = '82801I (ICH9 Family) USB UHCI Controller'
class = serial bus
subclass = USB
cap 13[50] = PCI Advanced Features: FLR TP
uhci5@pci0:0:29:2: class=0x0c0300 card=0x024d1028
chip=0x29368086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation'
device = '82801I (ICH9 Family) USB UHCI Controller'
class = serial bus
subclass = USB
cap 13[50] = PCI Advanced Features: FLR TP
ehci1@pci0:0:29:7: class=0x0c0320 card=0x024d1028
chip=0x293a8086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation'
device = '82801I (ICH9 Family) USB2 EHCI Controller'
class = serial bus
subclass = USB
cap 01[50] = powerspec 2 supports D0 D3 current D0
cap 0a[58] = EHCI Debug Port at offset 0xa0 in map 0x14
cap 13[98] = PCI Advanced Features: FLR TP
pcib3@pci0:0:30:0: class=0x060401 card=0x024d1028
chip=0x24488086 rev=0x93 hdr=0x01 vendor = 'Intel Corporation'
device = '82801 Mobile PCI Bridge'
class = bridge
subclass = PCI-PCI
cap 0d[50] = PCI Bridge card=0x024d1028
isab0@pci0:0:31:0: class=0x060100 card=0x024d1028
chip=0x29178086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation'
device = 'ICH9M-E LPC Interface Controller'
class = bridge
subclass = PCI-ISA
cap 09[e0] = vendor (length 12) Intel cap 1 version 0
features: SATA RAID-5, Mobile, 4 PCI-e x1 slots
ahci0@pci0:0:31:2: class=0x010601 card=0x024d1028
chip=0x29298086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation'
device = '82801IBM/IEM (ICH9M/ICH9M-E) 4 port SATA Controller
[AHCI mode]' class = mass storage
subclass = SATA
cap 05[80] = MSI supports 16 messages enabled with 16 messages
cap 01[70] = powerspec 3 supports D0 D3 current D0
cap 12[a8] = SATA Index-Data Pair
cap 13[b0] = PCI Advanced Features: FLR TP
none1@pci0:0:31:3: class=0x0c0500 card=0x024d1028
chip=0x29308086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation'
device = '82801I (ICH9 Family) SMBus Controller'
class = serial bus
subclass = SMBus
<[-------------]>
[=> END <=]
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