From owner-svn-src-head@FreeBSD.ORG Sun Nov 17 05:03:16 2013 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 4B4CD985; Sun, 17 Nov 2013 05:03:16 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 2234E2888; Sun, 17 Nov 2013 05:03:16 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id rAH53FR6033589; Sun, 17 Nov 2013 05:03:15 GMT (envelope-from nwhitehorn@svn.freebsd.org) Received: (from nwhitehorn@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id rAH53F27033585; Sun, 17 Nov 2013 05:03:15 GMT (envelope-from nwhitehorn@svn.freebsd.org) Message-Id: <201311170503.rAH53F27033585@svn.freebsd.org> From: Nathan Whitehorn Date: Sun, 17 Nov 2013 05:03:15 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r258250 - head/sys/powerpc/fpu X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Nov 2013 05:03:16 -0000 Author: nwhitehorn Date: Sun Nov 17 05:03:15 2013 New Revision: 258250 URL: http://svnweb.freebsd.org/changeset/base/258250 Log: Make single precision floating point arithmetic actually work -- I think it never did -- and fix an obvious missing line. Floating point emulation on Book-E still needs some work but this gets it basically functional on soft-FPU systems (hard FPU for Book-E is not yet implemented). MFC after: 1 week Modified: head/sys/powerpc/fpu/fpu_emu.c head/sys/powerpc/fpu/fpu_explode.c Modified: head/sys/powerpc/fpu/fpu_emu.c ============================================================================== --- head/sys/powerpc/fpu/fpu_emu.c Sun Nov 17 03:11:36 2013 (r258249) +++ head/sys/powerpc/fpu/fpu_emu.c Sun Nov 17 05:03:15 2013 (r258250) @@ -606,9 +606,11 @@ fpu_execute(struct trapframe *tf, struct rb = instr.i_a.i_frb; rc = instr.i_a.i_frc; - type = FTYPE_SNG; - if (instr.i_any.i_opcd & 0x4) - type = FTYPE_DBL; + /* + * All arithmetic operations work on registers, which + * are stored as doubles. + */ + type = FTYPE_DBL; switch ((unsigned int)instr.i_a.i_xo) { case OPC59_FDIVS: FPU_EMU_EVCNT_INCR(fdiv); @@ -725,6 +727,13 @@ fpu_execute(struct trapframe *tf, struct return (NOTFPU); break; } + + /* If the instruction was single precision, round */ + if (!(instr.i_any.i_opcd & 0x4)) { + fpu_implode(fe, fp, FTYPE_SNG, + (u_int *)&fs->fpreg[rt]); + fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); + } } } else { return (NOTFPU); Modified: head/sys/powerpc/fpu/fpu_explode.c ============================================================================== --- head/sys/powerpc/fpu/fpu_explode.c Sun Nov 17 03:11:36 2013 (r258249) +++ head/sys/powerpc/fpu/fpu_explode.c Sun Nov 17 05:03:15 2013 (r258250) @@ -235,6 +235,7 @@ fpu_explode(struct fpemu *fe, struct fpn s = fpu_dtof(fp, s, space[1]); break; + default: panic("fpu_explode"); panic("fpu_explode: invalid type %d", type); }