Date: Fri, 22 Jul 2016 17:34:28 +0000 (UTC) From: Ed Maste <emaste@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r303196 - in stable/11: contrib/llvm/projects/libunwind/include contrib/llvm/projects/libunwind/src gnu/lib/libgcc Message-ID: <201607221734.u6MHYSC0096506@repo.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: emaste Date: Fri Jul 22 17:34:28 2016 New Revision: 303196 URL: https://svnweb.freebsd.org/changeset/base/303196 Log: MFC libunwind improvements r302450: libunwind: update to upstream snapshot r272680 The key improvement is that it may be built without cross-unwinding support, which significantly reduces the stack space requirement. r302456: libunwind: enable only the native unwinder by default This significantly reduces stack space requirements, and runtimes require only native unwinding. r302475: libunwind: limit stack usage in unwind cursor This may be reworked upstream but in the interim should address the stack usage issue reported in the PR. r303016: llvm-libunwind: use conventional (non-Darwin) X86 register numbers For historical reasons Darwin/i386 has ebp and esp swapped in the eh_frame register numbering. That is: Darwin Other Reg # eh_frame eh_frame DWARF ===== ======== ======== ===== 4 ebp esp esp 5 esp ebp ebp Although the UNW_X86_* constants are not supposed to be coupled to DWARF / eh_frame numbering they are currently conflated in LLVM libunwind, and thus we require the non-Darwin numbering. PR: 206384 Approved by: re (kib) Sponsored by: The FreeBSD Foundation Modified: stable/11/contrib/llvm/projects/libunwind/include/__libunwind_config.h stable/11/contrib/llvm/projects/libunwind/include/libunwind.h stable/11/contrib/llvm/projects/libunwind/src/AddressSpace.hpp stable/11/contrib/llvm/projects/libunwind/src/CompactUnwinder.hpp stable/11/contrib/llvm/projects/libunwind/src/Registers.hpp stable/11/contrib/llvm/projects/libunwind/src/Unwind-EHABI.cpp stable/11/contrib/llvm/projects/libunwind/src/UnwindCursor.hpp stable/11/contrib/llvm/projects/libunwind/src/UnwindLevel1.c stable/11/contrib/llvm/projects/libunwind/src/UnwindRegistersRestore.S stable/11/contrib/llvm/projects/libunwind/src/UnwindRegistersSave.S stable/11/contrib/llvm/projects/libunwind/src/config.h stable/11/contrib/llvm/projects/libunwind/src/libunwind.cpp stable/11/gnu/lib/libgcc/Makefile Directory Properties: stable/11/ (props changed) Modified: stable/11/contrib/llvm/projects/libunwind/include/__libunwind_config.h ============================================================================== --- stable/11/contrib/llvm/projects/libunwind/include/__libunwind_config.h Fri Jul 22 17:31:14 2016 (r303195) +++ stable/11/contrib/llvm/projects/libunwind/include/__libunwind_config.h Fri Jul 22 17:34:28 2016 (r303196) @@ -17,4 +17,47 @@ #define _LIBUNWIND_ARM_EHABI 0 #endif +#if defined(_LIBUNWIND_IS_NATIVE_ONLY) +# if defined(__i386__) +# define _LIBUNWIND_TARGET_I386 1 +# define _LIBUNWIND_CONTEXT_SIZE 8 +# define _LIBUNWIND_CURSOR_SIZE 19 +# elif defined(__x86_64__) +# define _LIBUNWIND_TARGET_X86_64 1 +# define _LIBUNWIND_CONTEXT_SIZE 21 +# define _LIBUNWIND_CURSOR_SIZE 33 +# elif defined(__ppc__) +# define _LIBUNWIND_TARGET_PPC 1 +# define _LIBUNWIND_CONTEXT_SIZE 117 +# define _LIBUNWIND_CURSOR_SIZE 128 +# elif defined(__aarch64__) +# define _LIBUNWIND_TARGET_AARCH64 1 +# define _LIBUNWIND_CONTEXT_SIZE 66 +# define _LIBUNWIND_CURSOR_SIZE 78 +# elif defined(__arm__) +# define _LIBUNWIND_TARGET_ARM 1 +# define _LIBUNWIND_CONTEXT_SIZE 60 +# define _LIBUNWIND_CURSOR_SIZE 67 +# elif defined(__or1k__) +# define _LIBUNWIND_TARGET_OR1K 1 +# define _LIBUNWIND_CONTEXT_SIZE 16 +# define _LIBUNWIND_CURSOR_SIZE 28 +# elif defined(__riscv__) +# define _LIBUNWIND_TARGET_RISCV 1 +# define _LIBUNWIND_CONTEXT_SIZE 128 /* XXX */ +# define _LIBUNWIND_CURSOR_SIZE 140 /* XXX */ +# else +# error "Unsupported architecture." +# endif +#else // !_LIBUNWIND_IS_NATIVE_ONLY +# define _LIBUNWIND_TARGET_I386 1 +# define _LIBUNWIND_TARGET_X86_64 1 +# define _LIBUNWIND_TARGET_PPC 1 +# define _LIBUNWIND_TARGET_AARCH64 1 +# define _LIBUNWIND_TARGET_ARM 1 +# define _LIBUNWIND_TARGET_OR1K 1 +# define _LIBUNWIND_CONTEXT_SIZE 128 +# define _LIBUNWIND_CURSOR_SIZE 140 +#endif // _LIBUNWIND_IS_NATIVE_ONLY + #endif // ____LIBUNWIND_CONFIG_H__ Modified: stable/11/contrib/llvm/projects/libunwind/include/libunwind.h ============================================================================== --- stable/11/contrib/llvm/projects/libunwind/include/libunwind.h Fri Jul 22 17:31:14 2016 (r303195) +++ stable/11/contrib/llvm/projects/libunwind/include/libunwind.h Fri Jul 22 17:34:28 2016 (r303196) @@ -46,12 +46,12 @@ enum { }; struct unw_context_t { - uint64_t data[128]; + uint64_t data[_LIBUNWIND_CONTEXT_SIZE]; }; typedef struct unw_context_t unw_context_t; struct unw_cursor_t { - uint64_t data[140]; + uint64_t data[_LIBUNWIND_CURSOR_SIZE]; }; typedef struct unw_cursor_t unw_cursor_t; @@ -151,8 +151,8 @@ enum { UNW_X86_ECX = 1, UNW_X86_EDX = 2, UNW_X86_EBX = 3, - UNW_X86_EBP = 4, - UNW_X86_ESP = 5, + UNW_X86_ESP = 4, + UNW_X86_EBP = 5, UNW_X86_ESI = 6, UNW_X86_EDI = 7 }; @@ -295,77 +295,6 @@ enum { UNW_PPC_SPEFSCR = 112 }; -// 64-bit RISC-V registers -enum { - UNW_RISCV_X0 = 0, - UNW_RISCV_X1 = 1, - UNW_RISCV_RA = 1, - UNW_RISCV_X2 = 2, - UNW_RISCV_SP = 2, - UNW_RISCV_X3 = 3, - UNW_RISCV_X4 = 4, - UNW_RISCV_X5 = 5, - UNW_RISCV_X6 = 6, - UNW_RISCV_X7 = 7, - UNW_RISCV_X8 = 8, - UNW_RISCV_X9 = 9, - UNW_RISCV_X10 = 10, - UNW_RISCV_X11 = 11, - UNW_RISCV_X12 = 12, - UNW_RISCV_X13 = 13, - UNW_RISCV_X14 = 14, - UNW_RISCV_X15 = 15, - UNW_RISCV_X16 = 16, - UNW_RISCV_X17 = 17, - UNW_RISCV_X18 = 18, - UNW_RISCV_X19 = 19, - UNW_RISCV_X20 = 20, - UNW_RISCV_X21 = 21, - UNW_RISCV_X22 = 22, - UNW_RISCV_X23 = 23, - UNW_RISCV_X24 = 24, - UNW_RISCV_X25 = 25, - UNW_RISCV_X26 = 26, - UNW_RISCV_X27 = 27, - UNW_RISCV_X28 = 28, - UNW_RISCV_X29 = 29, - UNW_RISCV_X30 = 30, - UNW_RISCV_X31 = 31, - // reserved block - UNW_RISCV_D0 = 64, - UNW_RISCV_D1 = 65, - UNW_RISCV_D2 = 66, - UNW_RISCV_D3 = 67, - UNW_RISCV_D4 = 68, - UNW_RISCV_D5 = 69, - UNW_RISCV_D6 = 70, - UNW_RISCV_D7 = 71, - UNW_RISCV_D8 = 72, - UNW_RISCV_D9 = 73, - UNW_RISCV_D10 = 74, - UNW_RISCV_D11 = 75, - UNW_RISCV_D12 = 76, - UNW_RISCV_D13 = 77, - UNW_RISCV_D14 = 78, - UNW_RISCV_D15 = 79, - UNW_RISCV_D16 = 80, - UNW_RISCV_D17 = 81, - UNW_RISCV_D18 = 82, - UNW_RISCV_D19 = 83, - UNW_RISCV_D20 = 84, - UNW_RISCV_D21 = 85, - UNW_RISCV_D22 = 86, - UNW_RISCV_D23 = 87, - UNW_RISCV_D24 = 88, - UNW_RISCV_D25 = 89, - UNW_RISCV_D26 = 90, - UNW_RISCV_D27 = 91, - UNW_RISCV_D28 = 92, - UNW_RISCV_D29 = 93, - UNW_RISCV_D30 = 94, - UNW_RISCV_D31 = 95, -}; - // 64-bit ARM64 registers enum { UNW_ARM64_X0 = 0, @@ -604,4 +533,75 @@ enum { UNW_OR1K_R31 = 31, }; +// 64-bit RISC-V registers +enum { + UNW_RISCV_X0 = 0, + UNW_RISCV_X1 = 1, + UNW_RISCV_RA = 1, + UNW_RISCV_X2 = 2, + UNW_RISCV_SP = 2, + UNW_RISCV_X3 = 3, + UNW_RISCV_X4 = 4, + UNW_RISCV_X5 = 5, + UNW_RISCV_X6 = 6, + UNW_RISCV_X7 = 7, + UNW_RISCV_X8 = 8, + UNW_RISCV_X9 = 9, + UNW_RISCV_X10 = 10, + UNW_RISCV_X11 = 11, + UNW_RISCV_X12 = 12, + UNW_RISCV_X13 = 13, + UNW_RISCV_X14 = 14, + UNW_RISCV_X15 = 15, + UNW_RISCV_X16 = 16, + UNW_RISCV_X17 = 17, + UNW_RISCV_X18 = 18, + UNW_RISCV_X19 = 19, + UNW_RISCV_X20 = 20, + UNW_RISCV_X21 = 21, + UNW_RISCV_X22 = 22, + UNW_RISCV_X23 = 23, + UNW_RISCV_X24 = 24, + UNW_RISCV_X25 = 25, + UNW_RISCV_X26 = 26, + UNW_RISCV_X27 = 27, + UNW_RISCV_X28 = 28, + UNW_RISCV_X29 = 29, + UNW_RISCV_X30 = 30, + UNW_RISCV_X31 = 31, + // reserved block + UNW_RISCV_D0 = 64, + UNW_RISCV_D1 = 65, + UNW_RISCV_D2 = 66, + UNW_RISCV_D3 = 67, + UNW_RISCV_D4 = 68, + UNW_RISCV_D5 = 69, + UNW_RISCV_D6 = 70, + UNW_RISCV_D7 = 71, + UNW_RISCV_D8 = 72, + UNW_RISCV_D9 = 73, + UNW_RISCV_D10 = 74, + UNW_RISCV_D11 = 75, + UNW_RISCV_D12 = 76, + UNW_RISCV_D13 = 77, + UNW_RISCV_D14 = 78, + UNW_RISCV_D15 = 79, + UNW_RISCV_D16 = 80, + UNW_RISCV_D17 = 81, + UNW_RISCV_D18 = 82, + UNW_RISCV_D19 = 83, + UNW_RISCV_D20 = 84, + UNW_RISCV_D21 = 85, + UNW_RISCV_D22 = 86, + UNW_RISCV_D23 = 87, + UNW_RISCV_D24 = 88, + UNW_RISCV_D25 = 89, + UNW_RISCV_D26 = 90, + UNW_RISCV_D27 = 91, + UNW_RISCV_D28 = 92, + UNW_RISCV_D29 = 93, + UNW_RISCV_D30 = 94, + UNW_RISCV_D31 = 95, +}; + #endif Modified: stable/11/contrib/llvm/projects/libunwind/src/AddressSpace.hpp ============================================================================== --- stable/11/contrib/llvm/projects/libunwind/src/AddressSpace.hpp Fri Jul 22 17:31:14 2016 (r303195) +++ stable/11/contrib/llvm/projects/libunwind/src/AddressSpace.hpp Fri Jul 22 17:34:28 2016 (r303196) @@ -35,7 +35,7 @@ namespace libunwind { #include "Registers.hpp" #if _LIBUNWIND_ARM_EHABI -#if defined(__FreeBSD__) +#if defined(__FreeBSD__) || defined(__NetBSD__) #include <sys/link_elf.h> typedef void *_Unwind_Ptr; @@ -62,7 +62,8 @@ extern EHTEntry __exidx_end; #endif // !defined(_LIBUNWIND_IS_BAREMETAL) #endif // _LIBUNWIND_ARM_EHABI -#if defined(__CloudABI__) || defined(__FreeBSD__) || defined(__linux__) +#if defined(__CloudABI__) || defined(__FreeBSD__) || defined(__linux__) || \ + defined(__NetBSD__) #if _LIBUNWIND_SUPPORT_DWARF_UNWIND && _LIBUNWIND_SUPPORT_DWARF_INDEX #include <link.h> // Macro for machine-independent access to the ELF program headers. This Modified: stable/11/contrib/llvm/projects/libunwind/src/CompactUnwinder.hpp ============================================================================== --- stable/11/contrib/llvm/projects/libunwind/src/CompactUnwinder.hpp Fri Jul 22 17:31:14 2016 (r303195) +++ stable/11/contrib/llvm/projects/libunwind/src/CompactUnwinder.hpp Fri Jul 22 17:34:28 2016 (r303196) @@ -27,6 +27,7 @@ namespace libunwind { +#if defined(_LIBUNWIND_TARGET_I386) /// CompactUnwinder_x86 uses a compact unwind info to virtually "step" (aka /// unwind) by modifying a Registers_x86 register set template <typename A> @@ -255,8 +256,10 @@ void CompactUnwinder_x86<A>::framelessUn // old esp is before return address registers.setSP((uint32_t)returnAddressLocation + 4); } +#endif // _LIBUNWIND_TARGET_I386 +#if defined(_LIBUNWIND_TARGET_X86_64) /// CompactUnwinder_x86_64 uses a compact unwind info to virtually "step" (aka /// unwind) by modifying a Registers_x86_64 register set template <typename A> @@ -484,9 +487,11 @@ void CompactUnwinder_x86_64<A>::frameles // old esp is before return address registers.setSP(returnAddressLocation + 8); } +#endif // _LIBUNWIND_TARGET_X86_64 +#if defined(_LIBUNWIND_TARGET_AARCH64) /// CompactUnwinder_arm64 uses a compact unwind info to virtually "step" (aka /// unwind) by modifying a Registers_arm64 register set template <typename A> @@ -686,6 +691,7 @@ int CompactUnwinder_arm64<A>::stepWithCo return UNW_STEP_SUCCESS; } +#endif // _LIBUNWIND_TARGET_AARCH64 } // namespace libunwind Modified: stable/11/contrib/llvm/projects/libunwind/src/Registers.hpp ============================================================================== --- stable/11/contrib/llvm/projects/libunwind/src/Registers.hpp Fri Jul 22 17:31:14 2016 (r303195) +++ stable/11/contrib/llvm/projects/libunwind/src/Registers.hpp Fri Jul 22 17:34:28 2016 (r303196) @@ -25,6 +25,7 @@ namespace libunwind { struct v128 { uint32_t vec[4]; }; +#if defined(_LIBUNWIND_TARGET_I386) /// Registers_x86 holds the register state of a thread in a 32-bit intel /// process. class _LIBUNWIND_HIDDEN Registers_x86 { @@ -86,8 +87,8 @@ private: }; inline Registers_x86::Registers_x86(const void *registers) { - static_assert(sizeof(Registers_x86) < sizeof(unw_context_t), - "x86 registers do not fit into unw_context_t"); + static_assert((check_fit<Registers_x86, unw_context_t>::does_fit), + "x86 registers do not fit into unw_context_t"); memcpy(&_registers, registers, sizeof(_registers)); } @@ -211,8 +212,10 @@ inline v128 Registers_x86::getVectorRegi inline void Registers_x86::setVectorRegister(int, v128) { _LIBUNWIND_ABORT("no x86 vector registers"); } +#endif // _LIBUNWIND_TARGET_I386 +#if defined(_LIBUNWIND_TARGET_X86_64) /// Registers_x86_64 holds the register state of a thread in a 64-bit intel /// process. class _LIBUNWIND_HIDDEN Registers_x86_64 { @@ -278,8 +281,8 @@ private: }; inline Registers_x86_64::Registers_x86_64(const void *registers) { - static_assert(sizeof(Registers_x86_64) < sizeof(unw_context_t), - "x86_64 registers do not fit into unw_context_t"); + static_assert((check_fit<Registers_x86_64, unw_context_t>::does_fit), + "x86_64 registers do not fit into unw_context_t"); memcpy(&_registers, registers, sizeof(_registers)); } @@ -459,8 +462,10 @@ inline v128 Registers_x86_64::getVectorR inline void Registers_x86_64::setVectorRegister(int, v128) { _LIBUNWIND_ABORT("no x86_64 vector registers"); } +#endif // _LIBUNWIND_TARGET_X86_64 +#if defined(_LIBUNWIND_TARGET_PPC) /// Registers_ppc holds the register state of a thread in a 32-bit PowerPC /// process. class _LIBUNWIND_HIDDEN Registers_ppc { @@ -543,8 +548,8 @@ private: }; inline Registers_ppc::Registers_ppc(const void *registers) { - static_assert(sizeof(Registers_ppc) < sizeof(unw_context_t), - "ppc registers do not fit into unw_context_t"); + static_assert((check_fit<Registers_ppc, unw_context_t>::does_fit), + "ppc registers do not fit into unw_context_t"); memcpy(&_registers, static_cast<const uint8_t *>(registers), sizeof(_registers)); static_assert(sizeof(ppc_thread_state_t) == 160, @@ -1023,266 +1028,10 @@ inline const char *Registers_ppc::getReg } } - -/// Registers_riscv holds the register state of a thread in a 64-bit RISC-V -/// process. -class _LIBUNWIND_HIDDEN Registers_riscv { -public: - Registers_riscv(); - Registers_riscv(const void *registers); - - bool validRegister(int num) const; - uint64_t getRegister(int num) const; - void setRegister(int num, uint64_t value); - bool validFloatRegister(int num) const; - double getFloatRegister(int num) const; - void setFloatRegister(int num, double value); - bool validVectorRegister(int num) const; - v128 getVectorRegister(int num) const; - void setVectorRegister(int num, v128 value); - const char *getRegisterName(int num); - void jumpto(); - static int lastDwarfRegNum() { return 95; } - - uint64_t getSP() const { return _registers.__x[2]; } - void setSP(uint64_t value) { _registers.__x[2] = value; } - uint64_t getIP() const { return _registers.__x[1]; } - void setIP(uint64_t value) { _registers.__x[1] = value; } - -private: - struct GPRs { - uint64_t __x[32]; // x0-x31 - }; - - GPRs _registers; - double _vectorHalfRegisters[32]; - // Currently only the lower double in 128-bit vectore registers - // is perserved during unwinding. We could define new register - // numbers (> 96) which mean whole vector registers, then this - // struct would need to change to contain whole vector registers. -}; - -inline Registers_riscv::Registers_riscv(const void *registers) { - static_assert(sizeof(Registers_riscv) < sizeof(unw_context_t), - "riscv registers do not fit into unw_context_t"); - memcpy(&_registers, registers, sizeof(_registers)); - static_assert(sizeof(GPRs) == 0x100, - "expected VFP registers to be at offset 256"); - memcpy(_vectorHalfRegisters, - static_cast<const uint8_t *>(registers) + sizeof(GPRs), - sizeof(_vectorHalfRegisters)); -} - -inline Registers_riscv::Registers_riscv() { - memset(&_registers, 0, sizeof(_registers)); - memset(&_vectorHalfRegisters, 0, sizeof(_vectorHalfRegisters)); -} - -inline bool Registers_riscv::validRegister(int regNum) const { - if (regNum == UNW_REG_IP) - return true; - if (regNum == UNW_REG_SP) - return true; - if (regNum < 0) - return false; - if (regNum > 95) - return false; - if ((regNum > 31) && (regNum < 64)) - return false; - return true; -} - -inline uint64_t Registers_riscv::getRegister(int regNum) const { - if (regNum == UNW_REG_IP) - return _registers.__x[1]; - if (regNum == UNW_REG_SP) - return _registers.__x[2]; - if ((regNum >= 0) && (regNum < 32)) - return _registers.__x[regNum]; - _LIBUNWIND_ABORT("unsupported riscv register"); -} - -inline void Registers_riscv::setRegister(int regNum, uint64_t value) { - if (regNum == UNW_REG_IP) - _registers.__x[1] = value; - else if (regNum == UNW_REG_SP) - _registers.__x[2] = value; - else if ((regNum >= 0) && (regNum < 32)) - _registers.__x[regNum] = value; - else - _LIBUNWIND_ABORT("unsupported riscv register"); -} - -inline const char *Registers_riscv::getRegisterName(int regNum) { - switch (regNum) { - case UNW_REG_IP: - return "ra"; - case UNW_REG_SP: - return "sp"; - case UNW_RISCV_X0: - return "x0"; - case UNW_RISCV_X1: - return "ra"; - case UNW_RISCV_X2: - return "sp"; - case UNW_RISCV_X3: - return "x3"; - case UNW_RISCV_X4: - return "x4"; - case UNW_RISCV_X5: - return "x5"; - case UNW_RISCV_X6: - return "x6"; - case UNW_RISCV_X7: - return "x7"; - case UNW_RISCV_X8: - return "x8"; - case UNW_RISCV_X9: - return "x9"; - case UNW_RISCV_X10: - return "x10"; - case UNW_RISCV_X11: - return "x11"; - case UNW_RISCV_X12: - return "x12"; - case UNW_RISCV_X13: - return "x13"; - case UNW_RISCV_X14: - return "x14"; - case UNW_RISCV_X15: - return "x15"; - case UNW_RISCV_X16: - return "x16"; - case UNW_RISCV_X17: - return "x17"; - case UNW_RISCV_X18: - return "x18"; - case UNW_RISCV_X19: - return "x19"; - case UNW_RISCV_X20: - return "x20"; - case UNW_RISCV_X21: - return "x21"; - case UNW_RISCV_X22: - return "x22"; - case UNW_RISCV_X23: - return "x23"; - case UNW_RISCV_X24: - return "x24"; - case UNW_RISCV_X25: - return "x25"; - case UNW_RISCV_X26: - return "x26"; - case UNW_RISCV_X27: - return "x27"; - case UNW_RISCV_X28: - return "x28"; - case UNW_RISCV_X29: - return "x29"; - case UNW_RISCV_X30: - return "x30"; - case UNW_RISCV_X31: - return "x31"; - case UNW_RISCV_D0: - return "d0"; - case UNW_RISCV_D1: - return "d1"; - case UNW_RISCV_D2: - return "d2"; - case UNW_RISCV_D3: - return "d3"; - case UNW_RISCV_D4: - return "d4"; - case UNW_RISCV_D5: - return "d5"; - case UNW_RISCV_D6: - return "d6"; - case UNW_RISCV_D7: - return "d7"; - case UNW_RISCV_D8: - return "d8"; - case UNW_RISCV_D9: - return "d9"; - case UNW_RISCV_D10: - return "d10"; - case UNW_RISCV_D11: - return "d11"; - case UNW_RISCV_D12: - return "d12"; - case UNW_RISCV_D13: - return "d13"; - case UNW_RISCV_D14: - return "d14"; - case UNW_RISCV_D15: - return "d15"; - case UNW_RISCV_D16: - return "d16"; - case UNW_RISCV_D17: - return "d17"; - case UNW_RISCV_D18: - return "d18"; - case UNW_RISCV_D19: - return "d19"; - case UNW_RISCV_D20: - return "d20"; - case UNW_RISCV_D21: - return "d21"; - case UNW_RISCV_D22: - return "d22"; - case UNW_RISCV_D23: - return "d23"; - case UNW_RISCV_D24: - return "d24"; - case UNW_RISCV_D25: - return "d25"; - case UNW_RISCV_D26: - return "d26"; - case UNW_RISCV_D27: - return "d27"; - case UNW_RISCV_D28: - return "d28"; - case UNW_RISCV_D29: - return "d29"; - case UNW_RISCV_D30: - return "d30"; - case UNW_RISCV_D31: - return "d31"; - default: - return "unknown register"; - } -} - -inline bool Registers_riscv::validFloatRegister(int regNum) const { - if (regNum < UNW_RISCV_D0) - return false; - if (regNum > UNW_RISCV_D31) - return false; - return true; -} - -inline double Registers_riscv::getFloatRegister(int regNum) const { - assert(validFloatRegister(regNum)); - return _vectorHalfRegisters[regNum - UNW_RISCV_D0]; -} - -inline void Registers_riscv::setFloatRegister(int regNum, double value) { - assert(validFloatRegister(regNum)); - _vectorHalfRegisters[regNum - UNW_RISCV_D0] = value; -} - -inline bool Registers_riscv::validVectorRegister(int) const { - return false; -} - -inline v128 Registers_riscv::getVectorRegister(int) const { - _LIBUNWIND_ABORT("no riscv vector register support yet"); -} - -inline void Registers_riscv::setVectorRegister(int, v128) { - _LIBUNWIND_ABORT("no riscv vector register support yet"); -} +#endif // _LIBUNWIND_TARGET_PPC +#if defined(_LIBUNWIND_TARGET_AARCH64) /// Registers_arm64 holds the register state of a thread in a 64-bit arm /// process. class _LIBUNWIND_HIDDEN Registers_arm64 { @@ -1329,8 +1078,8 @@ private: }; inline Registers_arm64::Registers_arm64(const void *registers) { - static_assert(sizeof(Registers_arm64) < sizeof(unw_context_t), - "arm64 registers do not fit into unw_context_t"); + static_assert((check_fit<Registers_arm64, unw_context_t>::does_fit), + "arm64 registers do not fit into unw_context_t"); memcpy(&_registers, registers, sizeof(_registers)); static_assert(sizeof(GPRs) == 0x110, "expected VFP registers to be at offset 272"); @@ -1547,7 +1296,9 @@ inline v128 Registers_arm64::getVectorRe inline void Registers_arm64::setVectorRegister(int, v128) { _LIBUNWIND_ABORT("no arm64 vector register support yet"); } +#endif // _LIBUNWIND_TARGET_AARCH64 +#if defined(_LIBUNWIND_TARGET_ARM) /// Registers_arm holds the register state of a thread in a 32-bit arm /// process. /// @@ -1653,8 +1404,8 @@ inline Registers_arm::Registers_arm(cons _saved_vfp_d16_d31(false), _saved_iwmmx(false), _saved_iwmmx_control(false) { - static_assert(sizeof(Registers_arm) < sizeof(unw_context_t), - "arm registers do not fit into unw_context_t"); + static_assert((check_fit<Registers_arm, unw_context_t>::does_fit), + "arm registers do not fit into unw_context_t"); // See unw_getcontext() note about data. memcpy(&_registers, registers, sizeof(_registers)); memset(&_vfp_d0_d15_pad, 0, sizeof(_vfp_d0_d15_pad)); @@ -1969,6 +1720,10 @@ inline v128 Registers_arm::getVectorRegi inline void Registers_arm::setVectorRegister(int, v128) { _LIBUNWIND_ABORT("ARM vector support not implemented"); } +#endif // _LIBUNWIND_TARGET_ARM + + +#if defined(_LIBUNWIND_TARGET_OR1K) /// Registers_or1k holds the register state of a thread in an OpenRISC1000 /// process. class _LIBUNWIND_HIDDEN Registers_or1k { @@ -2003,8 +1758,8 @@ private: }; inline Registers_or1k::Registers_or1k(const void *registers) { - static_assert(sizeof(Registers_or1k) < sizeof(unw_context_t), - "or1k registers do not fit into unw_context_t"); + static_assert((check_fit<Registers_or1k, unw_context_t>::does_fit), + "or1k registers do not fit into unw_context_t"); memcpy(&_registers, static_cast<const uint8_t *>(registers), sizeof(_registers)); } @@ -2151,6 +1906,268 @@ inline const char *Registers_or1k::getRe } } +#endif // _LIBUNWIND_TARGET_OR1K + + +#if defined(_LIBUNWIND_TARGET_RISCV) +/// Registers_riscv holds the register state of a thread in a 64-bit RISC-V +/// process. +class _LIBUNWIND_HIDDEN Registers_riscv { +public: + Registers_riscv(); + Registers_riscv(const void *registers); + + bool validRegister(int num) const; + uint64_t getRegister(int num) const; + void setRegister(int num, uint64_t value); + bool validFloatRegister(int num) const; + double getFloatRegister(int num) const; + void setFloatRegister(int num, double value); + bool validVectorRegister(int num) const; + v128 getVectorRegister(int num) const; + void setVectorRegister(int num, v128 value); + const char *getRegisterName(int num); + void jumpto(); + static int lastDwarfRegNum() { return 95; } + + uint64_t getSP() const { return _registers.__x[2]; } + void setSP(uint64_t value) { _registers.__x[2] = value; } + uint64_t getIP() const { return _registers.__x[1]; } + void setIP(uint64_t value) { _registers.__x[1] = value; } + +private: + struct GPRs { + uint64_t __x[32]; // x0-x31 + }; + + GPRs _registers; + double _vectorHalfRegisters[32]; + // Currently only the lower double in 128-bit vectore registers + // is perserved during unwinding. We could define new register + // numbers (> 96) which mean whole vector registers, then this + // struct would need to change to contain whole vector registers. +}; + +inline Registers_riscv::Registers_riscv(const void *registers) { + static_assert((check_fit<Registers_riscv, unw_context_t>::does_fit), + "riscv registers do not fit into unw_context_t"); + memcpy(&_registers, registers, sizeof(_registers)); + static_assert(sizeof(GPRs) == 0x100, + "expected VFP registers to be at offset 256"); + memcpy(_vectorHalfRegisters, + static_cast<const uint8_t *>(registers) + sizeof(GPRs), + sizeof(_vectorHalfRegisters)); +} + +inline Registers_riscv::Registers_riscv() { + memset(&_registers, 0, sizeof(_registers)); + memset(&_vectorHalfRegisters, 0, sizeof(_vectorHalfRegisters)); +} + +inline bool Registers_riscv::validRegister(int regNum) const { + if (regNum == UNW_REG_IP) + return true; + if (regNum == UNW_REG_SP) + return true; + if (regNum < 0) + return false; + if (regNum > 95) + return false; + if ((regNum > 31) && (regNum < 64)) + return false; + return true; +} + +inline uint64_t Registers_riscv::getRegister(int regNum) const { + if (regNum == UNW_REG_IP) + return _registers.__x[1]; + if (regNum == UNW_REG_SP) + return _registers.__x[2]; + if ((regNum >= 0) && (regNum < 32)) + return _registers.__x[regNum]; + _LIBUNWIND_ABORT("unsupported riscv register"); +} + +inline void Registers_riscv::setRegister(int regNum, uint64_t value) { + if (regNum == UNW_REG_IP) + _registers.__x[1] = value; + else if (regNum == UNW_REG_SP) + _registers.__x[2] = value; + else if ((regNum >= 0) && (regNum < 32)) + _registers.__x[regNum] = value; + else + _LIBUNWIND_ABORT("unsupported riscv register"); +} + +inline const char *Registers_riscv::getRegisterName(int regNum) { + switch (regNum) { + case UNW_REG_IP: + return "ra"; + case UNW_REG_SP: + return "sp"; + case UNW_RISCV_X0: + return "x0"; + case UNW_RISCV_X1: + return "ra"; + case UNW_RISCV_X2: + return "sp"; + case UNW_RISCV_X3: + return "x3"; + case UNW_RISCV_X4: + return "x4"; + case UNW_RISCV_X5: + return "x5"; + case UNW_RISCV_X6: + return "x6"; + case UNW_RISCV_X7: + return "x7"; + case UNW_RISCV_X8: + return "x8"; + case UNW_RISCV_X9: + return "x9"; + case UNW_RISCV_X10: + return "x10"; + case UNW_RISCV_X11: + return "x11"; + case UNW_RISCV_X12: + return "x12"; + case UNW_RISCV_X13: + return "x13"; + case UNW_RISCV_X14: + return "x14"; + case UNW_RISCV_X15: + return "x15"; + case UNW_RISCV_X16: + return "x16"; + case UNW_RISCV_X17: + return "x17"; + case UNW_RISCV_X18: + return "x18"; + case UNW_RISCV_X19: + return "x19"; + case UNW_RISCV_X20: + return "x20"; + case UNW_RISCV_X21: + return "x21"; + case UNW_RISCV_X22: + return "x22"; + case UNW_RISCV_X23: + return "x23"; + case UNW_RISCV_X24: + return "x24"; + case UNW_RISCV_X25: + return "x25"; + case UNW_RISCV_X26: + return "x26"; + case UNW_RISCV_X27: + return "x27"; + case UNW_RISCV_X28: + return "x28"; + case UNW_RISCV_X29: + return "x29"; + case UNW_RISCV_X30: + return "x30"; + case UNW_RISCV_X31: + return "x31"; + case UNW_RISCV_D0: + return "d0"; + case UNW_RISCV_D1: + return "d1"; + case UNW_RISCV_D2: + return "d2"; + case UNW_RISCV_D3: + return "d3"; + case UNW_RISCV_D4: + return "d4"; + case UNW_RISCV_D5: + return "d5"; + case UNW_RISCV_D6: + return "d6"; + case UNW_RISCV_D7: + return "d7"; + case UNW_RISCV_D8: + return "d8"; + case UNW_RISCV_D9: + return "d9"; + case UNW_RISCV_D10: + return "d10"; + case UNW_RISCV_D11: + return "d11"; + case UNW_RISCV_D12: + return "d12"; + case UNW_RISCV_D13: + return "d13"; + case UNW_RISCV_D14: + return "d14"; + case UNW_RISCV_D15: + return "d15"; + case UNW_RISCV_D16: + return "d16"; + case UNW_RISCV_D17: + return "d17"; + case UNW_RISCV_D18: + return "d18"; + case UNW_RISCV_D19: + return "d19"; + case UNW_RISCV_D20: + return "d20"; + case UNW_RISCV_D21: + return "d21"; + case UNW_RISCV_D22: + return "d22"; + case UNW_RISCV_D23: + return "d23"; + case UNW_RISCV_D24: + return "d24"; + case UNW_RISCV_D25: + return "d25"; + case UNW_RISCV_D26: + return "d26"; + case UNW_RISCV_D27: + return "d27"; + case UNW_RISCV_D28: + return "d28"; + case UNW_RISCV_D29: + return "d29"; + case UNW_RISCV_D30: + return "d30"; + case UNW_RISCV_D31: + return "d31"; + default: + return "unknown register"; + } +} + +inline bool Registers_riscv::validFloatRegister(int regNum) const { + if (regNum < UNW_RISCV_D0) + return false; + if (regNum > UNW_RISCV_D31) + return false; + return true; +} + +inline double Registers_riscv::getFloatRegister(int regNum) const { + assert(validFloatRegister(regNum)); + return _vectorHalfRegisters[regNum - UNW_RISCV_D0]; +} + +inline void Registers_riscv::setFloatRegister(int regNum, double value) { + assert(validFloatRegister(regNum)); + _vectorHalfRegisters[regNum - UNW_RISCV_D0] = value; +} + +inline bool Registers_riscv::validVectorRegister(int) const { + return false; +} + +inline v128 Registers_riscv::getVectorRegister(int) const { + _LIBUNWIND_ABORT("no riscv vector register support yet"); +} + +inline void Registers_riscv::setVectorRegister(int, v128) { + _LIBUNWIND_ABORT("no riscv vector register support yet"); +} +#endif // _LIBUNWIND_TARGET_RISCV } // namespace libunwind #endif // __REGISTERS_HPP__ Modified: stable/11/contrib/llvm/projects/libunwind/src/Unwind-EHABI.cpp ============================================================================== --- stable/11/contrib/llvm/projects/libunwind/src/Unwind-EHABI.cpp Fri Jul 22 17:31:14 2016 (r303195) +++ stable/11/contrib/llvm/projects/libunwind/src/Unwind-EHABI.cpp Fri Jul 22 17:34:28 2016 (r303196) @@ -438,39 +438,21 @@ extern "C" _Unwind_Reason_Code __aeabi_u } static _Unwind_Reason_Code -unwind_phase1(unw_context_t *uc, _Unwind_Exception *exception_object) { +unwind_phase1(unw_context_t *uc, unw_cursor_t *cursor, _Unwind_Exception *exception_object) { // EHABI #7.3 discusses preserving the VRS in a "temporary VRS" during // phase 1 and then restoring it to the "primary VRS" for phase 2. The // effect is phase 2 doesn't see any of the VRS manipulations from phase 1. // In this implementation, the phases don't share the VRS backing store. // Instead, they are passed the original |uc| and they create a new VRS // from scratch thus achieving the same effect. - unw_cursor_t cursor1; - unw_init_local(&cursor1, uc); + unw_init_local(cursor, uc); // Walk each frame looking for a place to stop. for (bool handlerNotFound = true; handlerNotFound;) { -#if !_LIBUNWIND_ARM_EHABI - // Ask libuwind to get next frame (skip over first which is - // _Unwind_RaiseException). - int stepResult = unw_step(&cursor1); - if (stepResult == 0) { - _LIBUNWIND_TRACE_UNWINDING("unwind_phase1(ex_ojb=%p): unw_step() reached " - "bottom => _URC_END_OF_STACK\n", - static_cast<void *>(exception_object)); - return _URC_END_OF_STACK; - } else if (stepResult < 0) { - _LIBUNWIND_TRACE_UNWINDING("unwind_phase1(ex_ojb=%p): unw_step failed => " - "_URC_FATAL_PHASE1_ERROR\n", - static_cast<void *>(exception_object)); - return _URC_FATAL_PHASE1_ERROR; - } -#endif - // See if frame has code to run (has personality routine). unw_proc_info_t frameInfo; - if (unw_get_proc_info(&cursor1, &frameInfo) != UNW_ESUCCESS) { + if (unw_get_proc_info(cursor, &frameInfo) != UNW_ESUCCESS) { _LIBUNWIND_TRACE_UNWINDING("unwind_phase1(ex_ojb=%p): unw_get_proc_info " "failed => _URC_FATAL_PHASE1_ERROR\n", static_cast<void *>(exception_object)); @@ -482,12 +464,12 @@ unwind_phase1(unw_context_t *uc, _Unwind char functionBuf[512]; const char *functionName = functionBuf; unw_word_t offset; *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201607221734.u6MHYSC0096506>