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From: Peter Wemm <peter@FreeBSD.org>
To: Perforce Change Reviews <perforce@freebsd.org>
Cc: 
Subject: PERFORCE change 140243 for review
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http://perforce.freebsd.org/chv.cgi?CH=140243

Change 140243 by peter@peter_overcee on 2008/04/19 06:52:17

	Experiment with having the compiler round up the size of struct pcpu
	to 64 bytes, and arrange linker layout so that the members of "struct pcpu pcpu[MAXCPU]"
	are each on their own L1 cache line.

Affected files ...

.. //depot/projects/hammer/sys/amd64/include/pcpu.h#29 edit
.. //depot/projects/hammer/sys/i386/include/pcpu.h#16 edit
.. //depot/projects/hammer/sys/sys/pcpu.h#18 edit

Differences ...

==== //depot/projects/hammer/sys/amd64/include/pcpu.h#29 (text+ko) ====

@@ -53,6 +53,8 @@
 	register_t pc_fsbase;		/* User values of fsbase */	\
 	register_t pc_gsbase		/* User values of gsbase */
 
+#define PCPU_MD_ALIGN	__aligned(64)	/* use unique cache line per entry */
+
 #ifdef lint
 
 extern struct pcpu *pcpup;

==== //depot/projects/hammer/sys/i386/include/pcpu.h#16 (text+ko) ====

@@ -57,6 +57,8 @@
 	u_int	pc_apic_id;						\
 	int	pc_private_tss		/* Flag indicating private tss */
 
+#define PCPU_MD_ALIGN	__aligned(64)	/* max cache line size */
+
 #ifdef lint
 
 extern struct pcpu *pcpup;

==== //depot/projects/hammer/sys/sys/pcpu.h#18 (text+ko) ====

@@ -58,6 +58,10 @@
 	struct rm_queue* volatile rmq_prev;
 };
 
+#ifndef PCPU_MD_ALIGN
+#define PCPU_MD_ALIGN
+#endif
+
 /*
  * This structure maps out the global data that needs to be kept on a
  * per-cpu basis.  The members are accessed via the PCPU_GET/SET/PTR
@@ -104,7 +108,7 @@
 	 * If only to make kernel debugging easier...
 	 */
 	PCPU_MD_FIELDS;
-};
+} PCPU_MD_ALIGN;
 
 SLIST_HEAD(cpuhead, pcpu);