From owner-p4-projects@FreeBSD.ORG Sun Apr 22 20:08:17 2007 Return-Path: X-Original-To: p4-projects@freebsd.org Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 7E90816A408; Sun, 22 Apr 2007 20:08:17 +0000 (UTC) X-Original-To: perforce@freebsd.org Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 5C53C16A406 for ; Sun, 22 Apr 2007 20:08:17 +0000 (UTC) (envelope-from kmacy@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [69.147.83.41]) by mx1.freebsd.org (Postfix) with ESMTP id 4C50713C4D9 for ; Sun, 22 Apr 2007 20:08:17 +0000 (UTC) (envelope-from kmacy@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.13.8/8.13.8) with ESMTP id l3MK8HPK011424 for ; Sun, 22 Apr 2007 20:08:17 GMT (envelope-from kmacy@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.13.8/8.13.8/Submit) id l3MK8GAw011421 for perforce@freebsd.org; Sun, 22 Apr 2007 20:08:16 GMT (envelope-from kmacy@freebsd.org) Date: Sun, 22 Apr 2007 20:08:16 GMT Message-Id: <200704222008.l3MK8GAw011421@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to kmacy@freebsd.org using -f From: Kip Macy To: Perforce Change Reviews Cc: Subject: PERFORCE change 118602 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 22 Apr 2007 20:08:17 -0000 http://perforce.freebsd.org/chv.cgi?CH=118602 Change 118602 by kmacy@kmacy_vt-x:opentoe_init on 2007/04/22 20:07:53 Pull in changes to common files and latest firmware revision Affected files ... .. //depot/projects/opentoe/sys/dev/cxgb/common/cxgb_common.h#3 edit .. //depot/projects/opentoe/sys/dev/cxgb/common/cxgb_mc5.c#2 edit .. //depot/projects/opentoe/sys/dev/cxgb/common/cxgb_t3_cpl.h#2 edit .. //depot/projects/opentoe/sys/dev/cxgb/common/cxgb_t3_hw.c#3 edit .. //depot/projects/opentoe/sys/dev/cxgb/common/cxgb_version.h#3 edit .. //depot/projects/opentoe/sys/dev/cxgb/common/cxgb_xgmac.c#3 edit .. //depot/projects/opentoe/sys/dev/cxgb/t3fw-4.0.0.bin.gz#1 add .. //depot/projects/opentoe/sys/modules/cxgb/Makefile#5 edit Differences ... ==== //depot/projects/opentoe/sys/dev/cxgb/common/cxgb_common.h#3 (text+ko) ==== @@ -46,6 +46,7 @@ NMTUS = 16, /* size of MTU table */ NCCTRL_WIN = 32, /* # of congestion control windows */ NTX_SCHED = 8, /* # of HW Tx scheduling queues */ + TP_TMR_RES = 200, /* TP timer resolution in usec */ }; #define MAX_RX_COALESCING_LEN 16224U @@ -57,7 +58,6 @@ }; enum { - SUPPORTED_OFFLOAD = 1 << 24, SUPPORTED_IRQ = 1 << 25 }; @@ -70,8 +70,8 @@ }; enum { - FW_VERSION_MAJOR = 3, - FW_VERSION_MINOR = 2, + FW_VERSION_MAJOR = 4, + FW_VERSION_MINOR = 0, FW_VERSION_MICRO = 0 }; @@ -309,6 +309,9 @@ MC5_MODE_72_BIT = 2 }; +/* MC5 min active region size */ +enum { MC5_MIN_TIDS = 16 }; + struct vpd_params { unsigned int cclk; unsigned int mclk; @@ -354,6 +357,7 @@ unsigned int stats_update_period; /* MAC stats accumulation period */ unsigned int linkpoll_period; /* link poll period in 0.1s */ unsigned int rev; /* chip revision */ + unsigned int offload; }; enum { /* chip revisions */ @@ -427,8 +431,11 @@ adapter_t *adapter; unsigned int offset; unsigned int nucast; /* # of address filters for unicast MACs */ - unsigned int tcnt; - unsigned int xcnt; + unsigned int tx_tcnt; + unsigned int tx_xcnt; + u64 tx_mcnt; + unsigned int rx_xcnt; + u64 rx_mcnt; unsigned int toggle_cnt; unsigned int txen; struct mac_stats stats; @@ -555,7 +562,7 @@ static inline int is_offload(const adapter_t *adap) { #ifdef CONFIG_CHELSIO_T3_CORE - return adapter_info(adap)->caps & SUPPORTED_OFFLOAD; + return adap->params.offload; #else return 0; #endif ==== //depot/projects/opentoe/sys/dev/cxgb/common/cxgb_mc5.c#2 (text+ko) ==== @@ -329,6 +329,9 @@ unsigned int tcam_size = mc5->tcam_size; adapter_t *adap = mc5->adapter; + if (tcam_size == 0) + return 0; + if (nroutes > MAX_ROUTES || nroutes + nservers + nfilters > tcam_size) return -EINVAL; ==== //depot/projects/opentoe/sys/dev/cxgb/common/cxgb_t3_cpl.h#2 (text+ko) ==== @@ -260,6 +260,20 @@ #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT) #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT) +/* Applicable to BYPASS WRs only: the uP will added a CPL_BARRIER before + * and after the BYPASS WR if the ATOMIC bit is set. + */ +#define S_WR_ATOMIC 16 +#define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC) +#define F_WR_ATOMIC V_WR_ATOMIC(1U) + +/* Applicable to BYPASS WRs only: the uP will flush buffered non abort + * related WRs. + */ +#define S_WR_FLUSH 17 +#define V_WR_FLUSH(x) ((x) << S_WR_FLUSH) +#define F_WR_FLUSH V_WR_FLUSH(1U) + #define S_WR_DATATYPE 20 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE) #define F_WR_DATATYPE V_WR_DATATYPE(1U) @@ -1487,4 +1501,46 @@ #define M_TERM_TID 0xFFFFF #define V_TERM_TID(x) ((x) << S_TERM_TID) #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID) + +/* ULP_TX opcodes */ +enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 }; + +#define S_ULPTX_CMD 28 +#define M_ULPTX_CMD 0xF +#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) + +#define S_ULPTX_NFLITS 0 +#define M_ULPTX_NFLITS 0xFF +#define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS) + +struct ulp_mem_io { + WR_HDR; + __be32 cmd_lock_addr; + __be32 len; +}; + + /* ulp_mem_io.cmd_lock_addr fields */ +#define S_ULP_MEMIO_ADDR 0 +#define M_ULP_MEMIO_ADDR 0x7FFFFFF +#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) + +#define S_ULP_MEMIO_LOCK 27 +#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) +#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) + + /* ulp_mem_io.len fields */ +#define S_ULP_MEMIO_DATA_LEN 28 +#define M_ULP_MEMIO_DATA_LEN 0xF +#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) + +struct ulp_txpkt { + __be32 cmd_dest; + __be32 len; +}; + + /* ulp_txpkt.cmd_dest fields */ +#define S_ULP_TXPKT_DEST 24 +#define M_ULP_TXPKT_DEST 0xF +#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) + #endif /* T3_CPL_H */ ==== //depot/projects/opentoe/sys/dev/cxgb/common/cxgb_t3_hw.c#3 (text+ko) ==== @@ -441,23 +441,23 @@ { 2, 0, 0, 0, F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5, - SUPPORTED_OFFLOAD, + 0, &mi1_mdio_ops, "Chelsio PE9000" }, { 2, 0, 0, 0, F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, F_GPIO3 | F_GPIO5, - SUPPORTED_OFFLOAD, + 0, &mi1_mdio_ops, "Chelsio T302" }, { 1, 0, 0, 0, F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0, - SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_OFFLOAD, + SUPPORTED_10000baseT_Full | SUPPORTED_AUI, &mi1_mdio_ext_ops, "Chelsio T310" }, { 2, 0, 0, 0, F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 0, - SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_OFFLOAD, + SUPPORTED_10000baseT_Full | SUPPORTED_AUI, &mi1_mdio_ext_ops, "Chelsio T320" }, }; @@ -2387,9 +2387,6 @@ t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0); } -/* Desired TP timer resolution in usec */ -#define TP_TMR_RES 200 - /* TCP timer values in ms */ #define TP_DACK_TIMER 50 #define TP_RTO_MIN 250 @@ -3005,6 +3002,9 @@ adapter_t *adapter = mc7->adapter; const struct mc7_timing_params *p = &mc7_timings[mem_type]; + if (mc7->size == 0) + return 0; + val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); slow = val & F_SLOW; width = G_WIDTH(val); @@ -3209,9 +3209,10 @@ do { /* wait for uP to initialize */ t3_os_sleep(20); } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts); - if (!attempts) + if (!attempts) { + CH_ERR(adapter, "uP initialization timed out\n"); goto out_err; - + } err = 0; out_err: return err; @@ -3309,7 +3310,7 @@ mc7->name = name; mc7->offset = base_addr - MC7_PMRX_BASE_ADDR; cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); - mc7->size = mc7_calc_size(cfg); + mc7->size = G_DEN(cfg) == M_DEN ? 0 : mc7_calc_size(cfg); mc7->width = G_WIDTH(cfg); } @@ -3336,7 +3337,8 @@ V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1)); t3_write_reg(adapter, A_T3DBG_GPIO_EN, ai->gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL); - + t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0); + if (adapter->params.rev == 0 || !uses_xaui(adapter)) val |= F_ENRGMII; @@ -3435,7 +3437,12 @@ p->ntimer_qs = p->cm_size >= (128 << 20) || adapter->params.rev > 0 ? 12 : 6; p->dack_re = fls(adapter->params.vpd.cclk / 10) - 1; /* 100us */ + } + adapter->params.offload = t3_mc7_size(&adapter->pmrx) && + t3_mc7_size(&adapter->pmtx) && + t3_mc7_size(&adapter->cm); + if (is_offload(adapter)) { adapter->params.mc5.nservers = DEFAULT_NSERVERS; adapter->params.mc5.nfilters = adapter->params.rev > 0 ? DEFAULT_NFILTERS : 0; ==== //depot/projects/opentoe/sys/dev/cxgb/common/cxgb_version.h#3 (text+ko) ==== @@ -41,5 +41,5 @@ #define __CHELSIO_VERSION_H #define DRV_DESC "Chelsio T3 Network Driver" #define DRV_NAME "cxgb" -#define DRV_VERSION "1.0.071" -#endif +#define DRV_VERSION "1.0.086" +#endif ==== //depot/projects/opentoe/sys/dev/cxgb/common/cxgb_xgmac.c#3 (text+ko) ==== @@ -329,8 +329,8 @@ thres = mtu > thres ? (mtu - thres + 7) / 8 : 0; thres = max(thres, 8U); /* need at least 8 */ t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset, - V_TXFIFOTHRESH(M_TXFIFOTHRESH) | V_TXIPG(M_TXIPG), - V_TXFIFOTHRESH(thres) | V_TXIPG(1)); + V_TXFIFOTHRESH(M_TXFIFOTHRESH) | V_TXIPG(M_TXIPG), + V_TXFIFOTHRESH(thres) | V_TXIPG(1)); /* Assuming a minimum drain rate of 2.5Gbps... */ @@ -365,7 +365,7 @@ t3_set_reg_field(adap, A_XGM_PORT_CFG + oft, V_PORTSPEED(M_PORTSPEED), val); } -#if 0 +#if 0 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft); val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM); if (fc & PAUSE_TX) @@ -382,6 +382,7 @@ int idx = macidx(mac); adapter_t *adap = mac->adapter; unsigned int oft = mac->offset; + struct mac_stats *s = &mac->stats; if (which & MAC_DIRECTION_TX) { t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN); @@ -391,12 +392,20 @@ t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx); t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx); - mac->tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap, A_TP_PIO_DATA))); - mac->xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, A_XGM_TX_SPI4_SOP_EOP_CNT))); + mac->tx_mcnt = s->tx_frames; + mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap, + A_TP_PIO_DATA))); + mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, + A_XGM_TX_SPI4_SOP_EOP_CNT + + oft))); + mac->rx_mcnt = s->rx_frames; + mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, + A_XGM_RX_SPI4_SOP_EOP_CNT + + oft))); mac->txen = F_TXEN; mac->toggle_cnt = 0; } - if (which & MAC_DIRECTION_RX) + if (which & MAC_DIRECTION_RX) t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN); return 0; } @@ -405,6 +414,7 @@ { int idx = macidx(mac); adapter_t *adap = mac->adapter; + int val; if (which & MAC_DIRECTION_TX) { t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0); @@ -414,39 +424,99 @@ t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx); mac->txen = 0; } - if (which & MAC_DIRECTION_RX) + if (which & MAC_DIRECTION_RX) { + t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset, + F_PCS_RESET_, 0); + t3_os_sleep(100); t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0); + val = F_MAC_RESET_; + if (is_10G(adap)) + val |= F_PCS_RESET_; + else if (uses_xaui(adap)) + val |= F_PCS_RESET_ | F_XG2G_RESET_; + else + val |= F_RGMII_RESET_ | F_XG2G_RESET_; + t3_write_reg(mac->adapter, A_XGM_RESET_CTRL + mac->offset, val); + } return 0; } int t3b2_mac_watchdog_task(struct cmac *mac) { int status; - unsigned int tcnt, xcnt; + unsigned int tx_tcnt, tx_xcnt; adapter_t *adap = mac->adapter; - t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + macidx(mac)); - tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap, A_TP_PIO_DATA))); - xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, A_XGM_TX_SPI4_SOP_EOP_CNT + mac->offset))); + struct mac_stats *s = &mac->stats; + unsigned int tx_mcnt = (unsigned int)s->tx_frames; + unsigned int rx_mcnt = (unsigned int)s->rx_frames; + unsigned int rx_xcnt; + + status = 0; + tx_xcnt = 1; /* By default tx_xcnt is making progress*/ + tx_tcnt = mac->tx_tcnt; /* If tx_mcnt is progressing ignore tx_tcnt*/ + rx_xcnt = 1; /* By default rx_xcnt is making progress*/ + if (tx_mcnt == mac->tx_mcnt) { + tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, + A_XGM_TX_SPI4_SOP_EOP_CNT + + mac->offset))); + if (tx_xcnt == 0) { + t3_write_reg(adap, A_TP_PIO_ADDR, + A_TP_TX_DROP_CNT_CH0 + macidx(mac)); + tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap, + A_TP_PIO_DATA))); + } else { + goto rxcheck; + } + } else { + mac->toggle_cnt = 0; + goto rxcheck; + } - if ((tcnt != mac->tcnt) && (xcnt == 0) && (mac->xcnt == 0)) { + if (((tx_tcnt != mac->tx_tcnt) && + (tx_xcnt == 0) && (mac->tx_xcnt == 0)) || + ((mac->tx_mcnt == tx_mcnt) && + (tx_xcnt != 0) && (mac->tx_xcnt != 0))) { if (mac->toggle_cnt > 4) { - t3b2_mac_reset(mac); - mac->toggle_cnt = 0; status = 2; + goto out; } else { - t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0); - t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */ - t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen); - t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */ - mac->toggle_cnt++; status = 1; - } + goto out; + } } else { mac->toggle_cnt = 0; - status = 0; + goto rxcheck; + } + +rxcheck: + if (rx_mcnt != mac->rx_mcnt) + rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap, + A_XGM_RX_SPI4_SOP_EOP_CNT + + mac->offset))); + else + goto out; + + if (mac->rx_mcnt != s->rx_frames && rx_xcnt == 0 && mac->rx_xcnt == 0) { + status = 2; + goto out; + } + +out: + mac->tx_tcnt = tx_tcnt; + mac->tx_xcnt = tx_xcnt; + mac->tx_mcnt = s->tx_frames; + mac->rx_xcnt = rx_xcnt; + mac->rx_mcnt = s->rx_frames; + if (status == 1) { + t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0); + t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */ + t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen); + t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */ + mac->toggle_cnt++; + } else if (status == 2) { + t3b2_mac_reset(mac); + mac->toggle_cnt = 0; } - mac->tcnt = tcnt; - mac->xcnt = xcnt; return status; } ==== //depot/projects/opentoe/sys/modules/cxgb/Makefile#5 (text+ko) ==== @@ -14,12 +14,12 @@ .if ${MACHINE_ARCH} != "ia64" # ld is broken on ia64 -t3fw-3.2.bin: ${CXGB}/t3fw-3.2.bin.gz.uu - uudecode -p < ${CXGB}/t3fw-3.2.bin.gz.uu \ +t3fw-4.0.0.bin: ${CXGB}/t3fw-4.0.0.bin.gz.uu + uudecode -p < ${CXGB}/t3fw-4.0.0.bin.gz.uu \ | gzip -dc > ${.TARGET} -FIRMWS= t3fw-3.2.bin:t3fw32 -CLEANFILES+= t3fw-3.2.bin +FIRMWS= t3fw-4.0.0.bin:t3fw400 +CLEANFILES+= t3fw-4.0.0.bin .endif