Date: Sat, 13 Feb 2021 12:28:38 GMT From: Michal Meloun <mmel@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org Subject: git: 72d3aeb1b229 - releng/13.0 - arm32: Align arguments of sync_icache() syscall to cacheline size. Message-ID: <202102131228.11DCScd2048027@gitrepo.freebsd.org>
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The branch releng/13.0 has been updated by mmel: URL: https://cgit.FreeBSD.org/src/commit/?id=72d3aeb1b229d42d249bdd65105188a89b93218e commit 72d3aeb1b229d42d249bdd65105188a89b93218e Author: Michal Meloun <mmel@FreeBSD.org> AuthorDate: 2021-02-09 10:36:36 +0000 Commit: Michal Meloun <mmel@FreeBSD.org> CommitDate: 2021-02-13 12:27:43 +0000 arm32: Align arguments of sync_icache() syscall to cacheline size. Otherwise, we may miss synchronization of the last cacheline. Approved by: re (gjb) (cherry picked from commit ec090f4a67654fa541e6d97fd5f74d3f66c1c0d0) (cherry picked from commit 6930f97474e409808ca5e220c2b3a86805f786b8) --- sys/arm/arm/sys_machdep.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/sys/arm/arm/sys_machdep.c b/sys/arm/arm/sys_machdep.c index d33ac75ad73b..fc424d0fad39 100644 --- a/sys/arm/arm/sys_machdep.c +++ b/sys/arm/arm/sys_machdep.c @@ -68,12 +68,9 @@ sync_icache(uintptr_t addr, size_t len) size_t size; vm_offset_t rv; - /* - * Align starting address to even number because value of "1" - * is used as return value for success. - */ - len += addr & 1; - addr &= ~1; + /* Align starting address to cacheline size */ + len += addr & cpuinfo.dcache_line_mask; + addr &= ~cpuinfo.dcache_line_mask; /* Break whole range to pages. */ do {
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