From owner-freebsd-hackers@freebsd.org Tue Oct 27 13:51:08 2015 Return-Path: Delivered-To: freebsd-hackers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id C2DA2A1E7A2 for ; Tue, 27 Oct 2015 13:51:08 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from citadel.icyb.net.ua (citadel.icyb.net.ua [212.40.38.140]) by mx1.freebsd.org (Postfix) with ESMTP id D0AF01369; Tue, 27 Oct 2015 13:51:07 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from porto.starpoint.kiev.ua (porto-e.starpoint.kiev.ua [212.40.38.100]) by citadel.icyb.net.ua (8.8.8p3/ICyb-2.3exp) with ESMTP id PAA20802; Tue, 27 Oct 2015 15:50:59 +0200 (EET) (envelope-from avg@FreeBSD.org) Received: from localhost ([127.0.0.1]) by porto.starpoint.kiev.ua with esmtp (Exim 4.34 (FreeBSD)) id 1Zr4eQ-000HBQ-Qd; Tue, 27 Oct 2015 15:50:58 +0200 Subject: Re: instability of timekeeping To: Konstantin Belousov References: <56261398.60102@FreeBSD.org> <56261FE6.90302@FreeBSD.org> <56274FFC.2000608@FreeBSD.org> <20151021184850.GX2257@kib.kiev.ua> <562F3E2F.2010100@FreeBSD.org> <20151027115810.GU2257@kib.kiev.ua> Cc: freebsd-hackers , Poul-Henning Kamp , Jung-uk Kim From: Andriy Gapon Message-ID: <562F8109.4050203@FreeBSD.org> Date: Tue, 27 Oct 2015 15:50:01 +0200 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <20151027115810.GU2257@kib.kiev.ua> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Oct 2015 13:51:08 -0000 On 27/10/2015 13:58, Konstantin Belousov wrote: > On Tue, Oct 27, 2015 at 11:04:47AM +0200, Andriy Gapon wrote: >> And now another observation. I have C1E option enabled in BIOS. It >> means that if all cores enter C1 state, then the whole processor >> is magically placed into a deep C-state (C3, I think). LAPIC timer >> on this CPU model does not run in the deep C-state. So, I had to >> disable C1E option to test the LAPIC timer in a useful way. But >> before actually testing it I first tried to reproduce the problem. As >> you might have already guessed the problem is gone with that option >> disabled. Scratching my head to understand the implications of this >> observation. > > Most obvious explanation would be that the latency of wakeup is very large. > What is the HPET frequency when the jitter occur ? > kern.timecounter.tc.TSC-low.frequency: 1607351869 kern.eventtimer.et.HPET.frequency: 14318180 Or did you mean the actual rate of timer interrupts? -- Andriy Gapon