Date: Sun, 22 Sep 2002 21:23:50 -0700 (PDT) From: Peter Wemm <peter@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 17952 for review Message-ID: <200209230423.g8N4Nomt006985@freefall.freebsd.org>
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http://people.freebsd.org/~peter/p4db/chv.cgi?CH=17952 Change 17952 by peter@peter_overcee on 2002/09/22 21:23:27 update fxsave store area for 64 bit mode. instead of 8 xmm registers, there are 16. some segment:offset:pad groups became 64 bit pointers. Fix some errors in the x86 version. Affected files ... .. //depot/projects/hammer/sys/x86_64/include/npx.h#3 edit Differences ... ==== //depot/projects/hammer/sys/x86_64/include/npx.h#3 (text+ko) ==== @@ -79,16 +79,13 @@ struct envxmm { u_int16_t en_cw; /* control word (16bits) */ u_int16_t en_sw; /* status word (16bits) */ - u_int16_t en_tw; /* tag word (16bits) */ + u_int8_t en_tw; /* tag word (8bits) */ + u_int8_t en_zero; u_int16_t en_opcode; /* opcode last executed (11 bits ) */ - u_int32_t en_fip; /* floating point instruction pointer */ - u_int16_t en_fcs; /* floating code segment selector */ - u_int16_t en_pad0; /* padding */ - u_int32_t en_foo; /* floating operand offset */ - u_int16_t en_fos; /* floating operand segment selector */ - u_int16_t en_pad1; /* padding */ + u_int64_t en_rip; /* floating point instruction pointer */ + u_int64_t en_rdp; /* floating operand pointer */ u_int32_t en_mxcsr; /* SSE sontorol/status register */ - u_int32_t en_pad2; /* padding */ + u_int32_t en_mxcsr_mask; /* valid bits in mxcsr */ }; /* Contents of each SSE extended accumulator */ @@ -102,8 +99,8 @@ struct fpacc87 fp_acc; u_char fp_pad[6]; /* padding */ } sv_fp[8]; - struct xmmacc sv_xmm[8]; - u_char sv_pad[224]; + struct xmmacc sv_xmm[16]; + u_char sv_pad[96]; } __attribute__((aligned(16))); union savefpu { To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe p4-projects" in the body of the message
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