From owner-svn-src-projects@FreeBSD.ORG Tue Oct 23 17:13:46 2012 Return-Path: Delivered-To: svn-src-projects@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id B47CC3B7; Tue, 23 Oct 2012 17:13:46 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from citadel.icyb.net.ua (citadel.icyb.net.ua [212.40.38.140]) by mx1.freebsd.org (Postfix) with ESMTP id A31D18FC14; Tue, 23 Oct 2012 17:13:44 +0000 (UTC) Received: from odyssey.starpoint.kiev.ua (alpha-e.starpoint.kiev.ua [212.40.38.101]) by citadel.icyb.net.ua (8.8.8p3/ICyb-2.3exp) with ESMTP id UAA15107; Tue, 23 Oct 2012 20:13:37 +0300 (EEST) (envelope-from avg@FreeBSD.org) Message-ID: <5086D040.1090307@FreeBSD.org> Date: Tue, 23 Oct 2012 20:13:36 +0300 From: Andriy Gapon User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:16.0) Gecko/20121014 Thunderbird/16.0.1 MIME-Version: 1.0 To: Peter Grehan Subject: Re: svn commit: r241744 - projects/bhyve/usr.sbin/bhyve References: <201210191811.q9JIBIQu049356@svn.freebsd.org> <20121021121006.GA96141@stack.nl> <5085D433.4020101@freebsd.org> <20121023095549.GA27951@stack.nl> <5086C976.9060705@freebsd.org> In-Reply-To: <5086C976.9060705@freebsd.org> X-Enigmail-Version: 1.4.5 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cc: svn-src-projects@FreeBSD.org, src-committers@FreeBSD.org, Jilles Tjoelker X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 23 Oct 2012 17:13:46 -0000 on 23/10/2012 19:44 Peter Grehan said the following: > On 10/23/12 3:55 AM, Jilles Tjoelker wrote: >> On Mon, Oct 22, 2012 at 05:18:11PM -0600, Peter Grehan wrote: >>>> Case 4 looks wrong. A 32-bit write clears the top 32 bits of the >>>> register instead of preserving them. >> >>> Yep, you're right. How about: >> >>> > + case 4: >>> > + val = (reg & ~0xffffffffUL) | (operand & 0xffffffffUL); >>> > + break; >> >> I think you mean: >> val = operand & 0xffffffffUL; >> >> Right? > > Don't think so - the high 32 bits of the target register need to be or'd in, as > you originally mentioned. If this code emulates something like mov into %eax on AMDD64, then it should clear upper 32-bits of %rax. Which I think your original code already did, but in a less obvious way than Jilles suggested above. But I could be very well confused... -- Andriy Gapon