Date: Sat, 12 May 2012 20:36:12 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r235367 - head/sys/dev/etherswitch/arswitch Message-ID: <201205122036.q4CKaCpc051085@svn.freebsd.org>
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Author: adrian Date: Sat May 12 20:36:12 2012 New Revision: 235367 URL: http://svn.freebsd.org/changeset/base/235367 Log: * Add in the AR7240 global control field for setting the maximum frame size for the AR7240. * Include SM/MS macros, thanks to ath_hal(4). * This field is for normal packets, VLAN and other headers are added to this by the switch device. * Set the MTU to 1536, to match what is done in Linux. Use the SM macro to write this field. Obtained from: Atheros (AR7240 datasheet), Linux OpenWRT (MTU default) Modified: head/sys/dev/etherswitch/arswitch/arswitchreg.h Modified: head/sys/dev/etherswitch/arswitch/arswitchreg.h ============================================================================== --- head/sys/dev/etherswitch/arswitch/arswitchreg.h Sat May 12 20:34:22 2012 (r235366) +++ head/sys/dev/etherswitch/arswitch/arswitchreg.h Sat May 12 20:36:12 2012 (r235367) @@ -29,6 +29,15 @@ #ifndef __AR8X16_SWITCHREG_H__ #define __AR8X16_SWITCHREG_H__ +/* XXX doesn't belong here; stolen shamelessly from ath_hal/ah_internal.h */ +/* + * Register manipulation macros that expect bit field defines + * to follow the convention that an _S suffix is appended for + * a shift count, while the field mask has no suffix. + */ +#define SM(_v, _f) (((_v) << _f##_S) & (_f)) +#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) + /* Atheros specific MII registers */ #define MII_ATH_DBG_ADDR 0x1d #define MII_ATH_DBG_DATA 0x1e @@ -77,8 +86,13 @@ #define AR8X16_REG_GLOBAL_CTRL 0x0030 #define AR8216_GLOBAL_CTRL_MTU_MASK 0x00000fff +#define AR8216_GLOBAL_CTRL_MTU_MASK_S 0 #define AR8316_GLOBAL_CTRL_MTU_MASK 0x00007fff +#define AR8316_GLOBAL_CTRL_MTU_MASK_S 0 #define AR8236_GLOBAL_CTRL_MTU_MASK 0x00007fff +#define AR8236_GLOBAL_CTRL_MTU_MASK_S 0 +#define AR7240_GLOBAL_CTRL_MTU_MASK 0x00003fff +#define AR7240_GLOBAL_CTRL_MTU_MASK_S 0 #define AR8X16_REG_VLAN_CTRL 0x0040 #define AR8X16_VLAN_OP 0x00000007
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