From owner-freebsd-ports-bugs@FreeBSD.ORG Fri May 13 09:30:02 2005 Return-Path: Delivered-To: freebsd-ports-bugs@hub.freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id E9F4616A4CE for ; Fri, 13 May 2005 09:30:02 +0000 (GMT) Received: from freefall.freebsd.org (freefall.freebsd.org [216.136.204.21]) by mx1.FreeBSD.org (Postfix) with ESMTP id A049443D88 for ; Fri, 13 May 2005 09:30:02 +0000 (GMT) (envelope-from gnats@FreeBSD.org) Received: from freefall.freebsd.org (gnats@localhost [127.0.0.1]) by freefall.freebsd.org (8.13.3/8.13.3) with ESMTP id j4D9U2nF086849 for ; Fri, 13 May 2005 09:30:02 GMT (envelope-from gnats@freefall.freebsd.org) Received: (from gnats@localhost) by freefall.freebsd.org (8.13.3/8.13.1/Submit) id j4D9U2Y4086848; Fri, 13 May 2005 09:30:02 GMT (envelope-from gnats) Resent-Date: Fri, 13 May 2005 09:30:02 GMT Resent-Message-Id: <200505130930.j4D9U2Y4086848@freefall.freebsd.org> Resent-From: FreeBSD-gnats-submit@FreeBSD.org (GNATS Filer) Resent-To: freebsd-ports-bugs@FreeBSD.org Resent-Reply-To: FreeBSD-gnats-submit@FreeBSD.org, Ying-Chieh Liao Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id D597316A4CE for ; Fri, 13 May 2005 09:25:24 +0000 (GMT) Received: from FreeBSD.csie.NCTU.edu.tw (freebsd.csie.nctu.edu.tw [140.113.17.209]) by mx1.FreeBSD.org (Postfix) with ESMTP id 12B8643D7E for ; Fri, 13 May 2005 09:25:24 +0000 (GMT) (envelope-from ijliao@FreeBSD.csie.NCTU.edu.tw) Received: from localhost (unknown [127.0.0.1]) by FreeBSD.csie.NCTU.edu.tw (Postfix) with ESMTP id 05D0C106C42 for ; Fri, 13 May 2005 17:25:18 +0800 (CST) Received: from FreeBSD.csie.NCTU.edu.tw ([127.0.0.1]) by localhost (FreeBSD.csie.NCTU.edu.tw [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 85636-03 for ; Fri, 13 May 2005 17:25:16 +0800 (CST) Received: by FreeBSD.csie.NCTU.edu.tw (Postfix, from userid 1041) id B789A106C50; Fri, 13 May 2005 17:25:16 +0800 (CST) Message-Id: <20050513092516.B789A106C50@FreeBSD.csie.NCTU.edu.tw> Date: Fri, 13 May 2005 17:25:16 +0800 (CST) From: Ying-Chieh Liao To: FreeBSD-gnats-submit@FreeBSD.org X-Send-Pr-Version: 3.113 Subject: ports/80968: [NEW PORT] cad/gplcver: A Verilog HDL simulator X-BeenThere: freebsd-ports-bugs@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Ports bug reports List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 May 2005 09:30:03 -0000 >Number: 80968 >Category: ports >Synopsis: [NEW PORT] cad/gplcver: A Verilog HDL simulator >Confidential: no >Severity: non-critical >Priority: low >Responsible: freebsd-ports-bugs >State: open >Quarter: >Keywords: >Date-Required: >Class: change-request >Submitter-Id: current-users >Arrival-Date: Fri May 13 09:30:02 GMT 2005 >Closed-Date: >Last-Modified: >Originator: Ying-Chieh Liao >Release: FreeBSD 4.11-STABLE i386 >Organization: FreeBSD @ Taiwan >Environment: System: FreeBSD FreeBSD.csie.NCTU.edu.tw 4.11-STABLE FreeBSD 4.11-STABLE #3: Sat Apr 16 22:54:07 CST 2005 >Description: GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also implements some of the 2001 P1364 standard features including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language Reference Manual (LRM). Verilog is the name for both a language for describing electronic hardware called a hardware description language (HDL) and the name of the program that simulates HDL circuit descriptions to verify that described circuits will function correctly when the are constructed. Verilog is used only for describing digital logic circuits. Other HDLs such as Spice are used for describing analog circuits. There is an IEEE standard named P1364 that standardizes the Verilog HDL and the behavior of Verilog simulators. Verilog is officially defined in the IEEE P1364 Language Reference Manual (LRM) that can be purchased from IEEE. There are many good books for learning that teach the Verilog HDL and/or that teach digital circuit design using Verilog. WWW: http://www.pragmatic-c.com/gpl-cver/ Generated with FreeBSD Port Tools 0.63 >How-To-Repeat: >Fix: --- gplcver-2.10.c.shar begins here --- # This is a shell archive. Save it in a file, remove anything before # this line, and then unpack it by entering "sh file". Note, it may # create directories; files and directories will be owned by you and # have default permissions. # # This archive contains: # # gplcver # gplcver/Makefile # gplcver/distinfo # gplcver/pkg-descr # echo c - gplcver mkdir -p gplcver > /dev/null 2>&1 echo x - gplcver/Makefile sed 's/^X//' >gplcver/Makefile << 'END-of-gplcver/Makefile' X# ex:ts=8 X# Ports collection makefile for: gpl-cver X# Date created: May 13, 2005 X# Whom: ijliao X# X# $FreeBSD$ X# X XPORTNAME= gplcver XPORTVERSION= 2.10.c XCATEGORIES= cad XMASTER_SITES= http://www.pragmatic-c.com/gpl-cver/downloads/ XDISTNAME= ${PORTNAME}-${PORTVERSION:R}${PORTVERSION:E}.src X XMAINTAINER= ports@FreeBSD.org XCOMMENT= A Verilog HDL simulator X XUSE_BZIP2= yes XBUILD_WRKSRC= ${WRKSRC}/src XUSE_GMAKE= yes XMAKEFILE= makefile.freebsd X XPLIST_FILES= bin/cver X Xdo-install: X ${INSTALL_PROGRAM} ${WRKSRC}/bin/cver ${PREFIX}/bin X X.include END-of-gplcver/Makefile echo x - gplcver/distinfo sed 's/^X//' >gplcver/distinfo << 'END-of-gplcver/distinfo' XMD5 (gplcver-2.10c.src.tar.bz2) = e6221b7b9bfacf57dbdc1fca13e249de XSIZE (gplcver-2.10c.src.tar.bz2) = 1183806 END-of-gplcver/distinfo echo x - gplcver/pkg-descr sed 's/^X//' >gplcver/pkg-descr << 'END-of-gplcver/pkg-descr' XGPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also Ximplements some of the 2001 P1364 standard features including all three XPLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language XReference Manual (LRM). X XVerilog is the name for both a language for describing electronic hardware Xcalled a hardware description language (HDL) and the name of the program Xthat simulates HDL circuit descriptions to verify that described circuits Xwill function correctly when the are constructed. Verilog is used only for Xdescribing digital logic circuits. Other HDLs such as Spice are used for Xdescribing analog circuits. There is an IEEE standard named P1364 that Xstandardizes the Verilog HDL and the behavior of Verilog simulators. XVerilog is officially defined in the IEEE P1364 Language Reference XManual (LRM) that can be purchased from IEEE. There are many good books Xfor learning that teach the Verilog HDL and/or that teach digital circuit Xdesign using Verilog. X XWWW: http://www.pragmatic-c.com/gpl-cver/ END-of-gplcver/pkg-descr exit --- gplcver-2.10.c.shar ends here --- >Release-Note: >Audit-Trail: >Unformatted: