From owner-freebsd-arm@FreeBSD.ORG Tue Dec 17 17:55:27 2013 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 64849CD4; Tue, 17 Dec 2013 17:55:27 +0000 (UTC) Received: from smtpauth3.wiscmail.wisc.edu (wmauth3.doit.wisc.edu [144.92.197.226]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 31A141C90; Tue, 17 Dec 2013 17:55:26 +0000 (UTC) MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: text/plain; CHARSET=US-ASCII; format=flowed Received: from avs-daemon.smtpauth3.wiscmail.wisc.edu by smtpauth3.wiscmail.wisc.edu (Oracle Communications Messaging Server 7u4-27.01(7.0.4.27.0) 64bit (built Aug 30 2012)) id <0MXY00900P7YAT00@smtpauth3.wiscmail.wisc.edu>; Tue, 17 Dec 2013 11:55:25 -0600 (CST) X-Spam-PmxInfo: Server=avs-3, Version=6.0.3.2322014, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2013.12.17.174516, SenderIP=0.0.0.0 X-Spam-Report: AuthenticatedSender=yes, SenderIP=0.0.0.0 Received: from comporellon.tachypleus.net (adsl-76-208-69-44.dsl.mdsnwi.sbcglobal.net [76.208.69.44]) by smtpauth3.wiscmail.wisc.edu (Oracle Communications Messaging Server 7u4-27.01(7.0.4.27.0) 64bit (built Aug 30 2012)) with ESMTPSA id <0MXY001JUPSBV810@smtpauth3.wiscmail.wisc.edu>; Tue, 17 Dec 2013 11:55:24 -0600 (CST) Message-id: <52B0900B.7020905@freebsd.org> Date: Tue, 17 Dec 2013 11:55:23 -0600 From: Nathan Whitehorn User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:24.0) Gecko/20100101 Thunderbird/24.0 To: Zbigniew Bodek , "freebsd-arm@freebsd.org" Subject: Re: RFC: ARM related fixes - GIC, cache line size, PCI FDT & AHCI References: <52AF3D06.2000004@semihalf.com> <52AF760A.2030500@freebsd.org> In-reply-to: <52AF760A.2030500@freebsd.org> Cc: br@freebsd.org, Olivier Houchard X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Dec 2013 17:55:27 -0000 On 12/16/13 15:52, Nathan Whitehorn wrote: > On 12/16/13 11:48, Zbigniew Bodek wrote: >> Hello Everyone. >> >> We would like to submit some new patches recently developed by Semihalf. >> >> You can find them here: >> http://people.freebsd.org/~zbb/Semihalf/12.2013/ >> >> Detailed description is available in the commit logs but in general: >> >> -- 0001-Resolve-cache-line-size-using-CP15.patch >> - use cache line size acquired in runtime >> >> -- 0002-GIC-polarity-and-level-support.patch >> - suport for setting trigger level and polarity in GIC >> >> -- 0003-Add-PCI-FDT-interrupt-trigger-polarity-parsing.patch >> - trigger and polarity parsing for PCI FDT interrupts >> >> -- 0004-Do-not-attach-to-bridges-in-AHCI-driver.patch >> -- 0005-Use-only-mapped-BIOs-on-ARM.patch >> - Two patches enabling the AHCI driver on ARM chips >> >> >> We will appreciate if you could post your comments and/or remarks by the >> end of this week when we plan to commit the changes. >> >> Best regards >> zbb >> _______________________________________________ >> freebsd-arm@freebsd.org mailing list >> http://lists.freebsd.org/mailman/listinfo/freebsd-arm >> To unsubscribe, send any mail to "freebsd-arm-unsubscribe@freebsd.org" > > Can you hold off on > 0003-Add-PCI-FDT-interrupt-trigger-polarity-parsing.patch for the time > being? I'm restructuring this code at the moment. > -Nathan > _______________________________________________ > freebsd-arm@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-arm > To unsubscribe, send any mail to "freebsd-arm-unsubscribe@freebsd.org" This is done now. I have not updated the ARM code, because I don't know how it is supposed to work, but you can take a look at r259513 to powerpc/ofw/ofw_pci.c to see how the new stuff works. It relies on some device (nexus, for example) implementing OFW_BUS_CONFIG_INTR(), which takes an IRQ and a sense code, but that seems to be wrapped up in a lot of ARM-specific stuff. If you like, I can just write a piece of bridge code, but I don't want to interfere with in-flight things on your end. -Nathan