From owner-freebsd-arch Thu May 25 14: 0:35 2000 Delivered-To: freebsd-arch@freebsd.org Received: from alcanet.com.au (mail.alcanet.com.au [203.62.196.10]) by hub.freebsd.org (Postfix) with ESMTP id E245937B557; Thu, 25 May 2000 14:00:28 -0700 (PDT) (envelope-from jeremyp@pc0640.alcatel.com.au) Received: by border.alcanet.com.au id <115225>; Fri, 26 May 2000 07:00:36 +1000 From: Peter Jeremy Subject: Re: Preemptive kernel on older X86 hardware To: Mike Smith Cc: Terry Lambert , arch@FreeBSD.ORG Message-Id: <00May26.070036est.115225@border.alcanet.com.au> MIME-version: 1.0 X-Mailer: Mutt 1.0i Content-type: text/plain; charset=us-ascii Date: Fri, 26 May 2000 07:00:35 +1000 Sender: owner-freebsd-arch@FreeBSD.ORG Precedence: bulk X-Loop: FreeBSD.ORG On Thu, May 25, 2000 at 11:50:12AM +1000, Terry Lambert wrote: >What would be the "NOP" overhead on a pipelined instruction cache? On a 486, a NOP takes 1 cycle to execute. I suspect it's zero on the more recent processors. As Terry points out, there's also the fetch cost - but I-fetches are (effectively) free unless the processor bus is saturated. BTW, the IA32 has NOP's of various lengths. On the 486, single cycle NOPs can be 1, 2, 3 or 6 bytes long. There are also 5-byte almost-NOP (trash a register or flags) sequences. This means that a NOP sequence is fairly cheap. On Thu, May 25, 2000 at 12:13:43PM +1000, Mike Smith wrote: >> One I've been evilly considering is that the older processors >> lacking the instruction could simply take an instruction fault, > >This would only make sense if the fault handler patched the offending >code; it'd be too expensive otherwise. Not to mention having to make sure that the invalid opcode handler didn't need to access any locks. > I don't think this'd work on >i386, since the replacement code sequence is larger... You just have the larger code as the default and patch the smaller sequence if appropriate. Peter To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message