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Date:      Wed, 09 Dec 2020 12:44:42 +0100
From:      "Kristof Provost" <kp@FreeBSD.org>
To:        "Dimitry Andric" <dim@FreeBSD.org>
Cc:        freebsd-riscv@freebsd.org, toolchain@freebsd.org
Subject:   Re: devel/glib20 build issue
Message-ID:  <B2CCD4CE-3EE4-4D07-97A3-81E1C236AA71@FreeBSD.org>
In-Reply-To: <3BC510E6-F7FC-4341-B715-66472F3640BF@FreeBSD.org>
References:  <54177870-E411-4DF1-901E-94FE7E5F553F@FreeBSD.org> <3BC510E6-F7FC-4341-B715-66472F3640BF@FreeBSD.org>

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On 19 Nov 2020, at 11:59, Dimitry Andric wrote:
> On 19 Nov 2020, at 11:57, Kristof Provost <kp@freebsd.org> wrote:
>>
>> While trying to build assorted ports on RISC-V I found that 
>> devel/glib20 doesn’t build.
>> It turns out to be due to a missing 
>> __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 define. That define is implicitly 
>> set by the toolchain. Or, at least, it is on other platforms (ARM, 
>> MIPS, x86, …), but not on RISC-V.
>>
>> That’s likely just been forgotten. The following toolchain patch 
>> fixes that for me:
>>
>> 	diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp 
>> b/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
>> 	index 4ba703c8dd1..73f1b5bc446 100644
>> 	--- a/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
>> 	+++ b/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
>> 	@@ -115,8 +115,14 @@ void RISCVTargetInfo::getTargetDefines(const 
>> LangOptions &Opts,
>> 	     Builder.defineMacro("__riscv_muldiv");
>> 	   }
>>
>> 	-  if (HasA)
>> 	+  if (HasA) {
>> 	     Builder.defineMacro("__riscv_atomic");
>> 	+    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
>> 	+    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
>> 	+    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
>> 	+    if (Is64Bit)
>> 	+           
>> Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
>> 	+  }
>>
>> 	   if (HasF || HasD) {
>> 	     Builder.defineMacro("__riscv_flen", HasD ? "64" : "32");
>
> Hi Kristof,
>
> Can you please submit this upstream? We already have way too many 
> gratuitous RISC-V differences that haven't been upstreamed.
>
This https://reviews.llvm.org/D91784 got merged upstream. How do you 
feel about cherry-picking that into our tree? (I can do it, or you can, 
I don’t have feelings either way).

It’d fix building glib20 on RISC-V and unblock a bunch of ports. 
We’ll get it eventually though the next LLVM update, but I’m 
impatient.

Best regards,
Kristof



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