From owner-freebsd-current@FreeBSD.ORG Mon Apr 11 06:28:58 2005 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id D9BF816A4CE for ; Mon, 11 Apr 2005 06:28:58 +0000 (GMT) Received: from apollo.backplane.com (apollo.backplane.com [216.240.41.2]) by mx1.FreeBSD.org (Postfix) with ESMTP id B09E843D3F for ; Mon, 11 Apr 2005 06:28:58 +0000 (GMT) (envelope-from dillon@apollo.backplane.com) Received: from apollo.backplane.com (localhost [127.0.0.1]) j3B6Sw0e048328; Sun, 10 Apr 2005 23:28:58 -0700 (PDT) (envelope-from dillon@apollo.backplane.com) Received: (from dillon@localhost) by apollo.backplane.com (8.12.9p2/8.12.9/Submit) id j3B6Sw3m048327; Sun, 10 Apr 2005 23:28:58 -0700 (PDT) (envelope-from dillon) Date: Sun, 10 Apr 2005 23:28:58 -0700 (PDT) From: Matthew Dillon Message-Id: <200504110628.j3B6Sw3m048327@apollo.backplane.com> To: Scott Long References: <20050406233405.O47071@carver.gumbysoft.com> <200504081656.51917.jhb@FreeBSD.org> <20050410152946.W82708@carver.gumbysoft.com> <20050410172818.D82708@carver.gumbysoft.com> <200504110231.j3B2VOYr047361@apollo.backplane.com> <425A10DD.70500@samsco.org> cc: freebsd-current@freebsd.org Subject: Re: Potential source of interrupt aliasing X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Apr 2005 06:28:59 -0000 Sheesh Scott, you don't have to be nasty about it. I'm just trying to help. I've seen billions of interrupt routing related problems but not one interrupt aliasing issue. What I/O APIC chipset and stepping does Doug have on that motherboard? Intel has a ton of errata for their I/O APICs. I see a mention of having to turn off earlier revs of the chip and revert to legacy 'boot interrupt' operation, but that's the only mention I see, and it's only for old versions (< B-0 stepping) of the 80332. Still, perhaps the BIOS is doing this even with later revs of the chip in the MB. There's a reference to the '80332 I/O Processor' developers manual which implies a more detailed explanation of 'boot interrupt' operation. http://www.intel.com/design/iio/specupdt/27392703.pdf -Matt