From owner-p4-projects@FreeBSD.ORG Tue Mar 16 21:20:15 2010 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 3B8561065672; Tue, 16 Mar 2010 21:20:15 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id DBDDF106566C for ; Tue, 16 Mar 2010 21:20:14 +0000 (UTC) (envelope-from raj@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id C9E978FC19 for ; Tue, 16 Mar 2010 21:20:14 +0000 (UTC) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id o2GLKE5a097759 for ; Tue, 16 Mar 2010 21:20:14 GMT (envelope-from raj@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id o2GLKEgS097757 for perforce@freebsd.org; Tue, 16 Mar 2010 21:20:14 GMT (envelope-from raj@freebsd.org) Date: Tue, 16 Mar 2010 21:20:14 GMT Message-Id: <201003162120.o2GLKEgS097757@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to raj@freebsd.org using -f From: Rafal Jaworowski To: Perforce Change Reviews Precedence: bulk Cc: Subject: PERFORCE change 175743 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Mar 2010 21:20:15 -0000 http://p4web.freebsd.org/chv.cgi?CH=175743 Change 175743 by raj@raj_fdt on 2010/03/16 21:19:28 Improve and clean up FDT infrastructure on Marvell ARM. Affected files ... .. //depot/projects/fdt/sys/arm/mv/common.c#5 edit .. //depot/projects/fdt/sys/arm/mv/mvwin.h#2 edit Differences ... ==== //depot/projects/fdt/sys/arm/mv/common.c#5 (text+ko) ==== @@ -41,6 +41,7 @@ #include #include +#include #include #include @@ -91,6 +92,8 @@ u_long usb0_base = 0; u_long eth0_base = 0; u_long sata0_base = 0; +u_long idma0_base = 0; +u_long xor0_base = 0; static const struct decode_win *cpu_wins = cpu_win_tbl; @@ -104,6 +107,8 @@ { "mrvl,ge", ð0_base }, { "mrvl,usb-ehci", &usb0_base }, { "mrvl,sata", &sata0_base }, + { "mrvl,xor", &xor0_base}, + { "mrvl,idma", &idma0_base}, { NULL, NULL }, }; @@ -186,14 +191,14 @@ read_cpu_ctrl(uint32_t reg) { - return (bus_space_read_4(obio_tag, MV_CPU_CONTROL_BASE, reg)); + return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg)); } void write_cpu_ctrl(uint32_t reg, uint32_t val) { - bus_space_write_4(obio_tag, MV_CPU_CONTROL_BASE, reg, val); + bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); } void @@ -265,8 +270,8 @@ * possible) after the internal registers range has been mapped in via * pmap_devmap_bootstrap(). */ - *dev = bus_space_read_4(obio_tag, MV_PCIE_BASE, 0) >> 16; - *rev = bus_space_read_4(obio_tag, MV_PCIE_BASE, 8) & 0xff; + *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16; + *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff; } void @@ -396,11 +401,15 @@ #undef MV_CESA_BASE #undef MV_ETH0_BASE #undef MV_SATAHC_BASE +#undef MV_XOR_BASE +#undef MV_IDMA_BASE -#define MV_USB0_BASE (MV_BASE + usb0_base) -#define MV_CESA_BASE (MV_BASE + cesa_base) -#define MV_ETH0_BASE (MV_BASE + eth0_base) -#define MV_SATAHC_BASE (MV_BASE + sata0_base) +#define MV_USB0_BASE (FDT_IMMR_VA + usb0_base) +#define MV_CESA_BASE (FDT_IMMR_VA + cesa_base) +#define MV_ETH0_BASE (FDT_IMMR_VA + eth0_base) +#define MV_SATAHC_BASE (FDT_IMMR_VA + sata0_base) +#define MV_XOR_BASE (FDT_IMMR_VA + xor0_base) +#define MV_IDMA_BASE (FDT_IMMR_VA + idma0_base) /************************************************************************** * Decode windows registers accessors @@ -496,7 +505,7 @@ printf("\n"); } printf("Internal regs base: 0x%08x\n", - bus_space_read_4(obio_tag, MV_INTREGS_BASE, 0)); + bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0)); for (i = 0; i < MV_WIN_DDR_MAX; i++) printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i, @@ -1784,11 +1793,8 @@ if (fdt_get_regsize(node, &sram_base, &sram_size) != 0) return (EINVAL); - /* - * XXX Need to handle different CESA SRAM target ID accross SOCs. - */ - cpu_win_tbl[++t].target = 4; - cpu_win_tbl[t].attr = 0; + cpu_win_tbl[++t].target = MV_WIN_CESA_TARGET; + cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR; cpu_win_tbl[t].base = sram_base; cpu_win_tbl[t].size = sram_size; cpu_win_tbl[t].remap = -1; ==== //depot/projects/fdt/sys/arm/mv/mvwin.h#2 (text+ko) ==== @@ -167,6 +167,14 @@ #define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00) #define MV_WIN_CESA_MAX 4 +#if defined(SOC_MV_DISCOVERY) +#define MV_WIN_CESA_TARGET 9 +#define MV_WIN_CESA_ATTR 1 +#else +#define MV_WIN_CESA_TARGET 3 +#define MV_WIN_CESA_ATTR 0 +#endif + #define MV_WIN_USB_CTRL(n, m) (0x10 * (n) + (m) * 0x1000 + 0x0) #define MV_WIN_USB_BASE(n, m) (0x10 * (n) + (m) * 0x1000 + 0x4) #define MV_WIN_USB_MAX 4