Date: Sun, 2 May 2021 10:56:14 GMT From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 2420f6aed9e3 - main - Enable IPIs on CPU 0 on arm and arm64 Message-ID: <202105021056.142AuEUJ077009@gitrepo.freebsd.org>
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The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=2420f6aed9e355ff65377152ba977b3a5ac441d1 commit 2420f6aed9e355ff65377152ba977b3a5ac441d1 Author: Andrew Turner <andrew@FreeBSD.org> AuthorDate: 2021-05-02 07:43:34 +0000 Commit: Andrew Turner <andrew@FreeBSD.org> CommitDate: 2021-05-02 07:43:34 +0000 Enable IPIs on CPU 0 on arm and arm64 Not all interrupt controllers enable IPIs by default as the Arm GIC specs make it an implementation defined option. As at least two hypervisors have also previously masked the IPIs on boot. As we already enable these IPIs on the non-boot CPUs it is expected this is a safe operation. Differential Revision: https://reviews.freebsd.org/D26975 --- sys/arm64/arm64/mp_machdep.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sys/arm64/arm64/mp_machdep.c b/sys/arm64/arm64/mp_machdep.c index 8d5d82879571..3b1a8cc89cab 100644 --- a/sys/arm64/arm64/mp_machdep.c +++ b/sys/arm64/arm64/mp_machdep.c @@ -364,6 +364,8 @@ intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand, ii->ii_send_arg = isrc; strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN); ii->ii_count = intr_ipi_setup_counters(name); + + PIC_ENABLE_INTR(intr_irq_root_dev, isrc); } static void
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