From owner-freebsd-hardware Sat Jun 22 15:26:35 1996 Return-Path: owner-hardware Received: (from root@localhost) by freefall.freebsd.org (8.7.5/8.7.3) id PAA13544 for hardware-outgoing; Sat, 22 Jun 1996 15:26:35 -0700 (PDT) Received: from portal.spi.net ([199.238.225.153]) by freefall.freebsd.org (8.7.5/8.7.3) with SMTP id PAA13539 for ; Sat, 22 Jun 1996 15:26:33 -0700 (PDT) Received: from MindBender.HeadCandy.com (root@MindBender.HeadCandy.com [199.238.225.168]) by portal.spi.net (8.6.12/8.6.9) with ESMTP id PAA03558; Sat, 22 Jun 1996 15:26:28 -0700 Received: from localhost.HeadCandy.com (michaelv@localhost.HeadCandy.com [127.0.0.1]) by MindBender.HeadCandy.com (8.7.5/8.6.9) with SMTP id PAA11560; Sat, 22 Jun 1996 15:26:26 -0700 (PDT) Message-Id: <199606222226.PAA11560@MindBender.HeadCandy.com> X-Authentication-Warning: MindBender.HeadCandy.com: Host michaelv@localhost.HeadCandy.com [127.0.0.1] didn't use HELO protocol To: nash@mcs.com cc: freebsd-hardware@freebsd.org Subject: Re: Mixing SIMMs of different speeds In-reply-to: Your message of Sat, 22 Jun 96 17:21:04 -0500. <199606222221.RAA06668@zen.nash.org> Date: Sat, 22 Jun 1996 15:26:26 -0700 From: "Michael L. VanLoon -- HeadCandy.com" Sender: owner-hardware@freebsd.org X-Loop: FreeBSD.org Precedence: bulk >> >I'm wondering if I can mix 60 and 70ns SIMMs. Everyone says don't, >> >but they don't say why. I can understand not mixing SIMMs that will >> >be accessed simultaneously (like banks 1 and 2), but why shouldn't it >> >work when they are separated? My motherboard's manual indicates 70ns >> >or faster will work, so why wouldn't a mixture? >> Probably because the people who designed your motherboard designed its >> timing parameters with the assumption that all your memory would >> display consistent behavior. >The question is what behavior is it expecting? If it expects the data >to be valid within 70ns, it is consistent. Exactly. >> Another thing is that some motherboards will do interleaved access if >> you have matching size SIMMs in all the slots. This is where it >> alternates between accessing bank 1 and bank 2 on even/odd memory >> accesses. >Aren't both banks (1&2) accessed simultaneously for any 32-bit access? >When you said all slots, you mean groups of two, right? I was going under the assumption that one "bank" consists of the smallest usable memory size, i. e. two 72-pin SIMMs. So, bank 1 is the first pair of SIMMs, bank 2 the second.... >> If it were going to work at all, that would be my suggestion: put the >> slower memory first, so if it does some sort of test to see how fast >> your memory is, it might use the slower memory for the timings. Note >> that this is highly speculative and implementation specific. Only the >> people who designed your motherboard can tell you for sure. >Good, so I'm not crazy for thinking this might work :) Right -- this is what I would expect. But there's still no guarantee. Some engineer may have found it more useful to test, say, the last SIMM installed. How can we know without asking him? ----------------------------------------------------------------------------- Michael L. VanLoon michaelv@HeadCandy.com --< Free your mind and your machine -- NetBSD free un*x >-- NetBSD working ports: 386+PC, Mac 68k, Amiga, Atari 68k, HP300, Sun3, Sun4/4c/4m, DEC MIPS, DEC Alpha, PC532, VAX, MVME68k, arm32... NetBSD ports in progress: PICA, others... Roll your own Internet access -- Seattle People's Internet cooperative. If you're in the Seattle area, ask me how. -----------------------------------------------------------------------------