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Date:      Tue, 29 Aug 2000 21:17:29 +0200 (CEST)
From:      =?ISO-8859-1?Q?G=E9rard_Roudier?= <groudier@club-internet.fr>
To:        Hisashi Hiramoto <hiramoto@phys.chs.nihon-u.ac.jp>
Cc:        FreeBSD-bugs@FreeBSD.ORG
Subject:   Re: kern/20895: sym driver doesn't work for SYM53C895A
Message-ID:  <Pine.LNX.4.10.10008292055380.216-100000@linux.local>
In-Reply-To: <200008290332.e7T3WSm02626@march.phys.chs.nihon-u.ac.jp>

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On Tue, 29 Aug 2000, Hisashi Hiramoto wrote:

> Thanks for your quick response.
> 
> On Mon, 28 Aug 2000 22:51:01 +0200, =?ISO-8859-1?Q?G=E9rard_Roudier?= wrote in
> message-id <Pine.LNX.4.10.10008282234100.431-100000@linux.local>:
> > 
> > I just checked the docs and, indeed, the SYM53C895A is described as having
> > a PCI 32 bit interface, but supporting DAC access cycles. The patch above
> 
> I should have mentioned in the first bug report that 53c895a supports
> 32-bit PCI interface with 64-bit addressing.  Sorry to have forgotten
> to mention that.

No problem. It is maintainer's fault, so it is mine.

> # sym53c895a vs sym53c896 = i8088 vs i8086 ?

sym53c895a vs sym53c896/2 = i8088 vs i8086 ? seems more correct :-)
                       ^^
The patch below adds a new feature bit (FE_DAC) for 64 bit addressing
capability and fixes the chip descriptions accordingly, plus some minor
changes in the code (mostly FE_64BIT changed to FE_DAC).

You may check it (you seem to know well Symbios chips), do any additionnal
change I missed (if any), and report me if it works for you.

Thanks in advance,

  Gerard.


--- sym_defs.h.orig	Tue Aug 29 20:39:43 2000
+++ sym_defs.h	Tue Aug 29 20:40:02 2000
@@ -113,18 +113,19 @@
 #define FE_RAM		(1<<14)   /* On chip RAM present */
 #define FE_CLK80	(1<<15)   /* Board clock is 80 MHz */
 #define FE_RAM8K	(1<<16)   /* On chip RAM sized 8Kb */
-#define FE_64BIT	(1<<17)   /* Supports 64-bit addressing */
+#define FE_64BIT	(1<<17)   /* 64-bit PCI BUS interface */
 #define FE_IO256	(1<<18)   /* Requires full 256 bytes in PCI space */
 #define FE_NOPM		(1<<19)   /* Scripts handles phase mismatch */
 #define FE_LEDC		(1<<20)   /* Hardware control of LED */
 #define FE_ULTRA3	(1<<21)	  /* Ultra 3 - 80 Mtrans/sec DT */
-#define FE_PCI66	(1<<22)	  /* 66MHz PCI support */
+#define FE_66MHZ	(1<<22)	  /* 66MHz PCI support */
 #define FE_CRC		(1<<23)	  /* CRC support */
 #define FE_DIFF		(1<<24)	  /* SCSI HVD support */
 #define FE_DFBC		(1<<25)	  /* Have DFBC register */
 #define FE_LCKFRQ	(1<<26)	  /* Have LCKFRQ */
 #define FE_C10		(1<<27)	  /* Various C10 core (mis)features */
 #define FE_U3EN		(1<<28)	  /* U3EN bit usable */
+#define FE_DAC		(1<<29)	  /* Support PCI DAC (64 bit addressing) */
 
 #define FE_CACHE_SET	(FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
 #define FE_CACHE0_SET	(FE_CACHE_SET & ~FE_ERL)
--- sym_hipd.c.orig	Tue Aug 29 20:39:43 2000
+++ sym_hipd.c	Tue Aug 29 20:40:02 2000
@@ -2211,7 +2211,7 @@
 	if (chip->features & FE_LDSTR)
 		return &sym_fw2;
 #ifdef	SYM_CONF_GENERIC_SUPPORT
-	else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_64BIT)))
+	else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_DAC)))
 		return &sym_fw1;
 #endif
 	else
@@ -2787,9 +2787,9 @@
 	}
 	
 	/*
-	 *  64 bit (53C895A or 53C896) ?
+	 *  64 bit addressing  (895A/896/1010) ?
 	 */
-	if (np->features & FE_64BIT)
+	if (np->features & FE_DAC)
 #if BITS_PER_LONG > 32
 		np->rv_ccntl1	|= (XTIMOD | EXTIBMV);
 #else
@@ -3438,12 +3438,11 @@
 		np->rv_ccntl0 |= DPR;
 
 	/*
-	 *  If 64 bit (895A/896/1010) write CCNTL1 to enable 40 bit 
-	 *  address table indirect addressing for MOVE.
-	 *  Also write CCNTL0 if 64 bit chip, since this register seems 
-	 *  to only be used by 64 bit cores.
+	 *  Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing 
+	 *  and/or hardware phase mismatch, since only such chips 
+	 *  seem to support those IO registers.
 	 */
-	if (np->features & FE_64BIT) {
+	if (np->features & (FE_DAC|FE_NOPM)) {
 		OUTB (nc_ccntl0, np->rv_ccntl0);
 		OUTB (nc_ccntl1, np->rv_ccntl1);
 	}
@@ -8717,25 +8716,25 @@
 #endif
  {PCI_ID_SYM53C896, 0xff, "896", 6, 31, 7, 4,
  FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
- FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
+ FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
  ,
  {PCI_ID_SYM53C895A, 0xff, "895a", 6, 31, 7, 4,
  FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
- FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
+ FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
  ,
  {PCI_ID_LSI53C1010, 0x00, "1010-33", 6, 31, 7, 8,
  FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
- FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_PCI66|FE_CRC|
+ FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC|
  FE_C10}
  ,
  {PCI_ID_LSI53C1010, 0xff, "1010-33", 6, 31, 7, 8,
  FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
- FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC|
+ FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC|
  FE_C10|FE_U3EN}
  ,
  {PCI_ID_LSI53C1010_2, 0xff, "1010-66", 6, 31, 7, 8,
  FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
- FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_PCI66|FE_CRC|
+ FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC|
  FE_C10|FE_U3EN}
  ,
  {PCI_ID_LSI53C1510D, 0xff, "1510d", 6, 31, 7, 4,
----------------------------- Cut here -----------------------------------



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