From owner-svn-src-stable@freebsd.org Wed Nov 8 11:39:43 2017 Return-Path: Delivered-To: svn-src-stable@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id CA8A8E4FB43; Wed, 8 Nov 2017 11:39:43 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id A199975D59; Wed, 8 Nov 2017 11:39:43 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id vA8Bdgtk031635; Wed, 8 Nov 2017 11:39:42 GMT (envelope-from kib@FreeBSD.org) Received: (from kib@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id vA8BdgAn031630; Wed, 8 Nov 2017 11:39:42 GMT (envelope-from kib@FreeBSD.org) Message-Id: <201711081139.vA8BdgAn031630@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: kib set sender to kib@FreeBSD.org using -f From: Konstantin Belousov Date: Wed, 8 Nov 2017 11:39:42 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r325543 - in stable/10/sys: amd64/amd64 i386/i386 i386/isa X-SVN-Group: stable-10 X-SVN-Commit-Author: kib X-SVN-Commit-Paths: in stable/10/sys: amd64/amd64 i386/i386 i386/isa X-SVN-Commit-Revision: 325543 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 08 Nov 2017 11:39:43 -0000 Author: kib Date: Wed Nov 8 11:39:42 2017 New Revision: 325543 URL: https://svnweb.freebsd.org/changeset/base/325543 Log: MFC r325270: Consistently ensure that we do not load MXCSR with reserved bits set. Modified: stable/10/sys/amd64/amd64/fpu.c stable/10/sys/amd64/amd64/machdep.c stable/10/sys/i386/i386/machdep.c stable/10/sys/i386/isa/npx.c Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/amd64/amd64/fpu.c ============================================================================== --- stable/10/sys/amd64/amd64/fpu.c Wed Nov 8 11:25:19 2017 (r325542) +++ stable/10/sys/amd64/amd64/fpu.c Wed Nov 8 11:39:42 2017 (r325543) @@ -804,6 +804,7 @@ fpusetregs(struct thread *td, struct savefpu *addr, ch struct pcb *pcb; int error; + addr->sv_env.en_mxcsr &= cpu_mxcsr_mask; pcb = td->td_pcb; critical_enter(); if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { Modified: stable/10/sys/amd64/amd64/machdep.c ============================================================================== --- stable/10/sys/amd64/amd64/machdep.c Wed Nov 8 11:25:19 2017 (r325542) +++ stable/10/sys/amd64/amd64/machdep.c Wed Nov 8 11:39:42 2017 (r325543) @@ -2529,7 +2529,6 @@ static int set_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpustate, size_t xfpustate_len) { - struct savefpu *fpstate; int error; if (mcp->mc_fpformat == _MC_FPFMT_NODEV) @@ -2542,9 +2541,8 @@ set_fpcontext(struct thread *td, mcontext_t *mcp, char error = 0; } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || mcp->mc_ownedfp == _MC_FPOWNED_PCB) { - fpstate = (struct savefpu *)&mcp->mc_fpstate; - fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; - error = fpusetregs(td, fpstate, xfpustate, xfpustate_len); + error = fpusetregs(td, (struct savefpu *)&mcp->mc_fpstate, + xfpustate, xfpustate_len); } else return (EINVAL); return (error); Modified: stable/10/sys/i386/i386/machdep.c ============================================================================== --- stable/10/sys/i386/i386/machdep.c Wed Nov 8 11:25:19 2017 (r325542) +++ stable/10/sys/i386/i386/machdep.c Wed Nov 8 11:39:42 2017 (r325543) @@ -3932,7 +3932,6 @@ static int set_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpustate, size_t xfpustate_len) { - union savefpu *fpstate; int error; if (mcp->mc_fpformat == _MC_FPFMT_NODEV) @@ -3947,12 +3946,8 @@ set_fpcontext(struct thread *td, mcontext_t *mcp, char } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || mcp->mc_ownedfp == _MC_FPOWNED_PCB) { #ifdef DEV_NPX - fpstate = (union savefpu *)&mcp->mc_fpstate; -#ifdef CPU_ENABLE_SSE - if (cpu_fxsr) - fpstate->sv_xmm.sv_env.en_mxcsr &= cpu_mxcsr_mask; -#endif - error = npxsetregs(td, fpstate, xfpustate, xfpustate_len); + error = npxsetregs(td, (union savefpu *)&mcp->mc_fpstate, + xfpustate, xfpustate_len); #else error = EINVAL; #endif Modified: stable/10/sys/i386/isa/npx.c ============================================================================== --- stable/10/sys/i386/isa/npx.c Wed Nov 8 11:25:19 2017 (r325542) +++ stable/10/sys/i386/isa/npx.c Wed Nov 8 11:39:42 2017 (r325543) @@ -1124,6 +1124,10 @@ npxsetregs(struct thread *td, union savefpu *addr, cha if (!hw_float) return (ENXIO); +#ifdef CPU_ENABLE_SSE + if (cpu_fxsr) + addr->sv_xmm.sv_env.en_mxcsr &= cpu_mxcsr_mask; +#endif pcb = td->td_pcb; critical_enter(); if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {