From owner-svn-src-projects@FreeBSD.ORG Sun Oct 11 21:28:56 2009 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id E24B51065670; Sun, 11 Oct 2009 21:28:56 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id D24568FC19; Sun, 11 Oct 2009 21:28:56 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n9BLSu1Z031127; Sun, 11 Oct 2009 21:28:56 GMT (envelope-from gonzo@svn.freebsd.org) Received: (from gonzo@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n9BLSu0F031124; Sun, 11 Oct 2009 21:28:56 GMT (envelope-from gonzo@svn.freebsd.org) Message-Id: <200910112128.n9BLSu0F031124@svn.freebsd.org> From: Oleksandr Tymoshenko Date: Sun, 11 Oct 2009 21:28:56 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r197973 - projects/mips/sys/mips/atheros X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 11 Oct 2009 21:28:57 -0000 Author: gonzo Date: Sun Oct 11 21:28:56 2009 New Revision: 197973 URL: http://svn.freebsd.org/changeset/base/197973 Log: - Fix CPU divisor mask Repored by: Luiz Otavio O Souza Modified: projects/mips/sys/mips/atheros/ar71xxreg.h Modified: projects/mips/sys/mips/atheros/ar71xxreg.h ============================================================================== --- projects/mips/sys/mips/atheros/ar71xxreg.h Sun Oct 11 21:25:47 2009 (r197972) +++ projects/mips/sys/mips/atheros/ar71xxreg.h Sun Oct 11 21:28:56 2009 (r197973) @@ -143,7 +143,7 @@ #define PLL_DDR_DIV_SEL_SHIFT 18 #define PLL_DDR_DIV_SEL_MASK 3 #define PLL_CPU_DIV_SEL_SHIFT 16 -#define PLL_CPU_DIV_SEL_MASK 2 +#define PLL_CPU_DIV_SEL_MASK 3 #define PLL_LOOP_BW_SHIFT 12 #define PLL_LOOP_BW_MASK 0xf #define PLL_DIV_IN_SHIFT 10