From owner-svn-src-stable@FreeBSD.ORG Wed May 15 01:16:43 2013 Return-Path: Delivered-To: svn-src-stable@freebsd.org Received: from mx1.freebsd.org (mx1.FreeBSD.org [8.8.178.115]) by hub.freebsd.org (Postfix) with ESMTP id F0E06C2A; Wed, 15 May 2013 01:16:42 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id C903FB3E; Wed, 15 May 2013 01:16:42 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.6/8.14.6) with ESMTP id r4F1Ggn3084032; Wed, 15 May 2013 01:16:42 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.6/8.14.5/Submit) id r4F1GgHv084030; Wed, 15 May 2013 01:16:42 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <201305150116.r4F1GgHv084030@svn.freebsd.org> From: Pyun YongHyeon Date: Wed, 15 May 2013 01:16:42 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-9@freebsd.org Subject: svn commit: r250648 - stable/9/sys/dev/mii X-SVN-Group: stable-9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 May 2013 01:16:43 -0000 Author: yongari Date: Wed May 15 01:16:41 2013 New Revision: 250648 URL: http://svnweb.freebsd.org/changeset/base/250648 Log: MFC r248542: For RTL8211B or later PHYs, enable crossover detection and auto-correction. This change makes re(4) establish a link with a system using non-crossover UTP cable. Modified: stable/9/sys/dev/mii/rgephy.c stable/9/sys/dev/mii/rgephyreg.h Directory Properties: stable/9/sys/ (props changed) stable/9/sys/dev/ (props changed) Modified: stable/9/sys/dev/mii/rgephy.c ============================================================================== --- stable/9/sys/dev/mii/rgephy.c Wed May 15 01:06:24 2013 (r250647) +++ stable/9/sys/dev/mii/rgephy.c Wed May 15 01:16:41 2013 (r250648) @@ -488,7 +488,7 @@ rgephy_load_dspcode(struct mii_softc *sc static void rgephy_reset(struct mii_softc *sc) { - uint16_t ssr; + uint16_t pcr, ssr; if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev == 3) { /* RTL8211C(L) */ @@ -499,6 +499,15 @@ rgephy_reset(struct mii_softc *sc) } } + if (sc->mii_mpd_rev >= 2) { + pcr = PHY_READ(sc, RGEPHY_MII_PCR); + if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) { + pcr &= ~RGEPHY_PCR_MDI_MASK; + pcr |= RGEPHY_PCR_MDIX_AUTO; + PHY_WRITE(sc, RGEPHY_MII_PCR, pcr); + } + } + mii_phy_reset(sc); DELAY(1000); rgephy_load_dspcode(sc); Modified: stable/9/sys/dev/mii/rgephyreg.h ============================================================================== --- stable/9/sys/dev/mii/rgephyreg.h Wed May 15 01:06:24 2013 (r250647) +++ stable/9/sys/dev/mii/rgephyreg.h Wed May 15 01:16:41 2013 (r250648) @@ -138,6 +138,17 @@ #define RGEPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ /* RTL8211B(L)/RTL8211C(L) */ +#define RGEPHY_MII_PCR 0x10 /* PHY Specific control register */ +#define RGEPHY_PCR_ASSERT_CRS 0x0800 +#define RGEPHY_PCR_FORCE_LINK 0x0400 +#define RGEPHY_PCR_MDI_MASK 0x0060 +#define RGEPHY_PCR_MDIX_AUTO 0x0040 +#define RGEPHY_PCR_MDIX_MANUAL 0x0020 +#define RGEPHY_PCR_MDI_MANUAL 0x0000 +#define RGEPHY_PCR_CLK125_DIS 0x0010 +#define RGEPHY_PCR_JABBER_DIS 0x0001 + +/* RTL8211B(L)/RTL8211C(L) */ #define RGEPHY_MII_SSR 0x11 /* PHY Specific status register */ #define RGEPHY_SSR_S1000 0x8000 /* 1000Mbps */ #define RGEPHY_SSR_S100 0x4000 /* 100Mbps */