From owner-freebsd-hackers Wed Sep 6 13:00:11 1995 Return-Path: hackers-owner Received: (from majordom@localhost) by freefall.freebsd.org (8.6.11/8.6.6) id NAA09720 for hackers-outgoing; Wed, 6 Sep 1995 13:00:11 -0700 Received: from phaeton.artisoft.com (phaeton.Artisoft.COM [198.17.250.211]) by freefall.freebsd.org (8.6.11/8.6.6) with ESMTP id NAA09713 ; Wed, 6 Sep 1995 13:00:09 -0700 Received: (from terry@localhost) by phaeton.artisoft.com (8.6.11/8.6.9) id MAA00541; Wed, 6 Sep 1995 12:54:58 -0700 From: Terry Lambert Message-Id: <199509061954.MAA00541@phaeton.artisoft.com> Subject: Re: Cyrix cache enable patches? To: gibbs@freefall.freebsd.org (Justin T. Gibbs) Date: Wed, 6 Sep 1995 12:54:58 -0700 (MST) Cc: hackers@freefall.freebsd.org In-Reply-To: <199509061746.KAA14927@freefall.freebsd.org> from "Justin T. Gibbs" at Sep 6, 95 10:46:40 am X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Length: 622 Sender: hackers-owner@FreeBSD.org Precedence: bulk > > Did anyone look at integrating these patches? Cyrix doesn't honor the non-cacheable bit. It would be silly to integrate patches to turn it on without integrating detect as a global setting and doing a BINVD when a read is issued to get around it not honoring the non-cacheable bit. You *aren't* going to get a cache update, since the motherboard chipset doesn't notify the chip of a bus mastering DMA causing a cache invalidation to be necessary (no pin on the chip for it). Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.